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Digital Electronics
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Integrated Circuit Technologies
Comments
Question
PMOS and NMOS circuits are used largely in ________.
Options
A. MSI functions
B. LSI functions
C. diode functions
D. TTL functions
Correct Answer
LSI functions
Integrated Circuit Technologies problems
Search Results
1. In a TTL circuit, if an excessive number of load gate inputs are connected, ________.
Options
A. V
OH(min)
drops below V
OH
B. V
OH
drops below V
OH(min)
C. V
OH
exceeds V
OH(min)
D. V
OH
and V
OH(min)
are unaffected
Show Answer
Scratch Pad
Discuss
Correct Answer: V
OH
drops below V
OH(min)
2. The active switching element used in all TTL circuits is the ________.
Options
A. bipolar junction transistor (BJT)
B. field-effect transistor (FET)
C. metal-oxide semiconductor field-effect transistor (MOSFET)
D. unijunction transistor (UJ)
Show Answer
Scratch Pad
Discuss
Correct Answer: bipolar junction transistor (BJT)
3. TTL is alive and well, particularly in ________.
Options
A. industrial applications
B. educational applications
C. military applications
D. commercial applications
Show Answer
Scratch Pad
Discuss
Correct Answer: educational applications
4. An open-collector output requires ________.
Options
A. a pull-down resistor
B. a pull-up resistor
C. no output resistor
D. an output resistor
Show Answer
Scratch Pad
Discuss
Correct Answer: a pull-up resistor
5. For a CMOS gate, which is the best speed-power product?
Options
A. 1.4 pJ
B. 1.6 pJ
C. 2.4 pJ
D. 3.3 pJ
Show Answer
Scratch Pad
Discuss
Correct Answer: 1.4 pJ
6. Which is not an output state for tristate logic?
Options
A. HIGH
B. LOW
C. High-Z
D. Low-Z
Show Answer
Scratch Pad
Discuss
Correct Answer: Low-Z
7. A TTL NAND gate with I
IH(max)
of 40 µA per input drives ten TTL inputs. How much current does the drive output source?
Options
A. 40 µA
B. 200 µA
C. 400 µA
D. 800 µA
Show Answer
Scratch Pad
Discuss
Correct Answer: 400 µA
8. An open-drain gate is the CMOS counterpart of ________.
Options
A. an open-collector TTL gate
B. a tristate TTL gate
C. a bipolar junction transistor
D. an emitter-coupled logic gate
Show Answer
Scratch Pad
Discuss
Correct Answer: an open-collector TTL gate
9. Which factor does not affect CMOS loading?
Options
A. Charging time associated with the output resistance of the driving gate
B. Discharging time associated with the output resistance of the driving gate
C. Output capacitance of the load gates
D. Input capacitance of the load gates
Show Answer
Scratch Pad
Discuss
Correct Answer: Output capacitance of the load gates
10. A certain gate draws 1.8 µA when its output is HIGH and 3.3 µA when its output is LOW. V
CC
is 5 V and the gate is operated on a 50% duty cycle. What is the average power dissipation (P
D
)?
Options
A. 2.55 µW
B. 1.27 µW
C. 12.75 µW
D. 5 µW
Show Answer
Scratch Pad
Discuss
Correct Answer: 12.75 µW
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