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  • Question
  • Which logic family combines the advantages of CMOS and TTL?


  • Options
  • A. BiCMOS
  • B. TTL/CMOS
  • C. ECL
  • D. TTL/MOS

  • Correct Answer
  • BiCMOS 


  • Integrated Circuit Technologies problems


    Search Results


    • 1. Most TTL logic used today is some form of ________.

    • Options
    • A. Schottky TTL
    • B. tristate TTL
    • C. low-power TTL
    • D. open-collector TTL
    • Discuss
    • 2. The greater the propagation delay, the ________.

    • Options
    • A. lower the maximum frequency
    • B. higher the maximum frequency
    • C. maximum frequency is unaffected
    • D. minimum frequency is unaffected
    • Discuss
    • 3. A TTL NAND gate with IIL(max) of ?1.6 mA per input drives eight TTL inputs. How much current does the drive output sink?

    • Options
    • A. ?12.8 mA
    • B. ?8 mA
    • C. ?1.6 mA
    • D. ?25.6 mA
    • Discuss
    • 4. What is the speed of the up/down digital-ramp ADC (tracking ADC)?

    • Options
    • A. 20 µs
    • B. 10 µs
    • C. 1 µs
    • D. Relatively slow
    • Discuss
    • 5. The primary disadvantage of the simultaneous A/D converter is:

    • Options
    • A. that it requires the input voltage to be applied to the inputs simultaneously
    • B. the long conversion time required
    • C. the large number of output lines required to simultaneously decode the input voltage
    • D. the large number of comparators required to represent a reasonable sized binary number
    • Discuss
    • 6. Which is not part of emitter-coupled logic (ECL)?

    • Options
    • A. Differential amplifier
    • B. Bias circuit
    • C. Emitter-follower circuit
    • D. Totem-pole circuit
    • Discuss
    • 7. Which transistor element is used in CMOS logic?

    • Options
    • A. FET
    • B. MOSFET
    • C. Bipolar
    • D. Unijunction
    • Discuss
    • 8. Which is not a MOSFET terminal?

    • Options
    • A. Gate
    • B. Drain
    • C. Source
    • D. Base
    • Discuss
    • 9. Which equation is correct?

    • Options
    • A. VNL = VIL(max) + VOL(max)
    • B. VNH = VOH(min) + VIH(min)
    • C. VNL = VOH(min) ? VIH(min)
    • D. VNH = VOH(min) ? VIH(min)
    • Discuss
    • 10. A standard TTL circuit with a totem-pole output can sink, in the LOW state (IOL(max)), ________.

    • Options
    • A. 16 mA
    • B. 20 mA
    • C. 16 µA
    • D. 20 µA
    • Discuss


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