L1 is known as ________. primary cache secondary cache DRAM SRAM

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primary cache

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1. Select the statement that best describes Read-Only Memory (ROM).
Options
A. nonvolatile, used to store information that changes during system operation
B. nonvolatile, used to store information that does not change during system operation
C. volatile, used to store information that changes during system operation
D. volatile, used to store information that does not change during system operation

2. The device shown in the given figure is checked with a logic probe and the output is HIGH.
Options
A. The device is working properly.
B. For the input conditions shown the output should be LOW; the input is shorted to ground.
C. For the input conditions shown the output should be neither HIGH nor LOW; the device is shorted to .
D. The device is probably alright; the problem is most likely caused by the stage connected to the output of the device.

3. The check sum method of testing a ROM:
Options
A. indicates if the data in more than one memory location is incorrect.
B. provides a means for locating and correcting data errors in specific memory locations.
C. allows data errors to be pinpointed to a specific memory location.
D. simply indicates that the contents of the ROM are incorrect.

6. Select the statement that best describes the fusible-link PROM.
Options
A. user-programmable, one-time programmable
B. manufacturer-programmable, one-time programmable
C. user-programmable, reprogrammable
D. manufacturer-programmable, reprogrammable

7. The RAM circuit given below is suspected of being bad. A check with a logic probe shows pulse activity on all of the address lines and data inputs. The / line and inputs are forced HIGH and the data output lines are checked with the logic probe. Q0, Q2, and Q3 show a dim indication on the logic probe; Q1 indicates a HIGH level on the logic probe. What, if anything, is wrong with the circuit?
Options
A. The Q0, Q2, and Q3 output lines are open; the chip is defective.
B. The Q1 line appears to be shorted to V_cc; replace the chip.
C. The outputs should be active only when the / line is held LOW, so the circuit is behaving normally considering the fact that the line is HIGH.
D. The EN input should be forced HIGH and the outputs rechecked; if they are still giving the same indications as before, then the three outputs are definitely open and the IC will have to be replaced.

10. Which of the following faults will the checkerboard pattern test for in RAM?
Options
A. Short between adjacent cells
B. Ability to store both 0s and 1s
C. Dynamically introduced errors between cells
D. All of the above

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