How many storage locations are available when a memory device has 12 address lin

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Question
How many storage locations are available when a memory device has 12 address lines?
Options
A. 144
B. 512
C. 2048
D. 4096

Correct Answer

4096

Memory and Storage problems

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1. EEPROM stands for ________.
Options
A. encapsulated electrical programmable read-only memory
B. elementary electrical programmable read-only memory
C. electrically erasable programmable read-only memory
D. elementary erasable programmable read-only memory

3. What is the meaning of RAM, and what is its primary role?
Options
A. Readily Available Memory; it is the first level of memory used by the computer in all of its operations.
B. Random Access Memory; it is memory that can be reached by any sub- system within a computer, and at any time.
C. Random Access Memory; it is the memory used for short-term temporary data storage within the computer.
D. Resettable Automatic Memory; it is memory that can be used and then automatically reset, or cleared, after being read from or written to.

4. Which of the following best describes random-access memory (RAM)?
Options
A. a type of memory in which access time depends on memory location
B. a type of memory that can be written to only once but can be read from an infinite number of times
C. a type of memory in which access time is the same for each memory location
D. mass memory

5. A CD-R disk is created by applying heat to special chemicals on the disk and these chemicals reflect less light than the areas that are not burned, thus creating the same effect as a pit does on a regular CD.
Options
A. True
B. False

6. A major disadvantage of the mask ROM is that it:
Options
A. is time consuming to change the stored data when system requirements change
B. is very expensive to change the stored data when system requirements change
C. cannot be reprogrammed if stored data needs to be changed
D. has an extremely short life expectancy and requires frequent replacement

8. What is the principal advantage of using address multiplexing with DRAM memory?
Options
A. reduced memory access time
B. reduced requirement for constant refreshing of the memory contents
C. reduced pin count and decrease in package size
D. It eliminates the requirement for a chip-select input line, thereby reducing the pin count.

10. Refer the given figure. The outputs (Q0?Q3) of the memory are always LOW. The address lines (A0?A7) are checked with a logic probe and all are indicating pulse activity, except for A3, which shows a constant HIGH, and A7, which shows a constant LOW; the select lines, are checked and shows pulse activity, while indicates a constant HIGH. What is wrong, and how can the memory be tested to determine whether it is defective or if the external circuitry is defective?
Options
A. One of the inputs to the active-LOW select AND gate may be stuck high for some reason; take both select lines LOW and check for pulse activity on the outputs, Q0?Q3. If the outputs now respond, the problem is most likely in the program or circuitry driving the select lines.
B. The problem appears to be in the two address lines that never change levels; the problem is probably in the program driving the memory address bus.
C. The output buffers are probably defective since they are all tied together; the common input line is most likely stuck LOW. Change the output buffer IC.
D. Since no data appears to be getting through to the output buffers, the problem may be in the X decoder; change the X decoder IC.

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