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Digital Electronics
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Digital Arithmetic Operations and Circuits
Comments
Question
How many inputs must a full-adder have?
Options
A. 2
B. 3
C. 4
D. 5
Correct Answer
3
Tags:
Bank Exams
Digital Arithmetic Operations and Circuits problems
Search Results
1. The binary subtraction 0 ? 0 =
Options
A. difference = 0
borrow = 0
B. difference = 1
borrow = 0
C. difference = 1
borrow = 1
D. difference = 0
borrow = 1
Show Answer
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Discuss
Correct Answer: difference = 0
borrow = 0
2. Add the following hex numbers: 0110
16
+ 10010
16
Options
A. 10120
16
B. 10020
16
C. 11120
16
D. 00120
16
Show Answer
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Discuss
Correct Answer: 10120
16
3. Convert each of the decimal numbers to 8-bit two's-complement form and then perform subtraction by taking the two's-complement and adding.
Options
A. 0001 0011
B. 0000 1110
C. 0010 1110
D. 1110 0000
Show Answer
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Discuss
Correct Answer: 0000 1110
4. Which of the following is correct for full adders?
Options
A. Full adders have the capability of directly adding decimal numbers.
B. Full adders are used to make half adders.
C. Full adders are limited to two inputs since there are only two binary digits.
D. In a parallel full adder, the first stage may be a half adder.
Show Answer
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Correct Answer: In a parallel full adder, the first stage may be a half adder.
5. The carry propagation delay in 4-bit full-adder circuits:
Options
A. is cumulative for each stage and limits the speed at which arithmetic operations are performed
B. is normally not a consideration because the delays are usually in the nanosecond range
C. decreases in direct ratio to the total number of full-adder stages
D. increases in direct ratio to the total number of full-adder stages, but is not a factor in limiting the speed of arithmetic operations
Show Answer
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Correct Answer: is cumulative for each stage and limits the speed at which arithmetic operations are performed
6. The summing outputs of a half- or full-adder are designated by which Greek symbol?
Options
A. omega
B. theta
C. lambda
D. sigma
Show Answer
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Correct Answer: sigma
7. What is one disadvantage of the ripple-carry adder?
Options
A. The interconnections are more complex.
B. More stages are required to a full adder.
C. It is slow due to propagation time.
D. All of the above.
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Correct Answer: It is slow due to propagation time.
8. When 1100010 is divided by 0101, what is the decimal remainder?
Options
A. 2
B. 3
C. 4
D. 6
Show Answer
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Discuss
Correct Answer: 3
9. With a 50 kHz clock frequency, six bits can be serially entered into a shift register in ________.
Options
A. 12 µs
B. 120 µs
C. 12 ms
D. 120 ms
Show Answer
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Correct Answer: 120 µs
10. Ring shift and Johnson counters are:
Options
A. synchronous counters
B. aynchronous counters
C. true binary counters
D. synchronous and true binary counters
Show Answer
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Discuss
Correct Answer: synchronous counters
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