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  • Question
  • How many inputs must a full-adder have?


  • Options
  • A. 2
  • B. 3
  • C. 4
  • D. 5

  • Correct Answer


  • Tags: Bank Exams

    Digital Arithmetic Operations and Circuits problems


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    • 1. The binary subtraction 0 ? 0 =

    • Options
    • A. difference = 0
      borrow = 0
    • B. difference = 1
      borrow = 0
    • C. difference = 1
      borrow = 1
    • D. difference = 0
      borrow = 1
    • Discuss
    • 2. Add the following hex numbers: 011016 + 1001016

    • Options
    • A. 1012016
    • B. 1002016
    • C. 1112016
    • D. 0012016
    • Discuss
    • 3. Convert each of the decimal numbers to 8-bit two's-complement form and then perform subtraction by taking the two's-complement and adding.


    • Options
    • A. 0001  0011
    • B. 0000  1110
    • C. 0010  1110
    • D. 1110  0000
    • Discuss
    • 4. Which of the following is correct for full adders?

    • Options
    • A. Full adders have the capability of directly adding decimal numbers.
    • B. Full adders are used to make half adders.
    • C. Full adders are limited to two inputs since there are only two binary digits.
    • D. In a parallel full adder, the first stage may be a half adder.
    • Discuss
    • 5. The carry propagation delay in 4-bit full-adder circuits:

    • Options
    • A. is cumulative for each stage and limits the speed at which arithmetic operations are performed
    • B. is normally not a consideration because the delays are usually in the nanosecond range
    • C. decreases in direct ratio to the total number of full-adder stages
    • D. increases in direct ratio to the total number of full-adder stages, but is not a factor in limiting the speed of arithmetic operations
    • Discuss
    • 6. The summing outputs of a half- or full-adder are designated by which Greek symbol?

    • Options
    • A. omega
    • B. theta
    • C. lambda
    • D. sigma
    • Discuss
    • 7. What is one disadvantage of the ripple-carry adder?

    • Options
    • A. The interconnections are more complex.
    • B. More stages are required to a full adder.
    • C. It is slow due to propagation time.
    • D. All of the above.
    • Discuss
    • 8. When 1100010 is divided by 0101, what is the decimal remainder?

    • Options
    • A. 2
    • B. 3
    • C. 4
    • D. 6
    • Discuss
    • 9. With a 50 kHz clock frequency, six bits can be serially entered into a shift register in ________.

    • Options
    • A. 12 µs
    • B. 120 µs
    • C. 12 ms
    • D. 120 ms
    • Discuss
    • 10. Ring shift and Johnson counters are:

    • Options
    • A. synchronous counters
    • B. aynchronous counters
    • C. true binary counters
    • D. synchronous and true binary counters
    • Discuss


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