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- Question
The truth table for a full adder is shown below. What are the values of X, Y, and Z?
Options- A. X = 0, Y = 1, Z = 1
- B. X = 1, Y = 1, Z = 1
- C. X = 1, Y = 0, Z = 1
- D. X = 0, Y = 0, Z = 1
- Correct Answer
- X = 1, Y = 1, Z = 1
- 1. Solve this BCD problem: 0100 + 0110 =
Options- A. 00010000BCD
- B. 00010111BCD
- C. 00001011BCD
- D. 00010011BCD Discuss
- 2. The two's-complement system is to be used to add the signed numbers 11110010 and 11110011. Determine, in decimal, the sign and value of each number and their sum.
Options- A. ?14 and ?13, ?27
- B. ?113 and ?114, 227
- C. ?27 and ?13, 40
- D. ?11 and ?16, ?27 Discuss
- 3. One way to make a four-bit adder perform subtraction is by:
Options- A. inverting the output.
- B. inverting the carry-in.
- C. inverting the B inputs.
- D. grounding the B inputs. Discuss
- 4. Solve this binary problem: 01000110 ÷ 00001010 =
Options- A. 0111
- B. 10011
- C. 1001
- D. 0011 Discuss
- 5. Solve the following:
Options- A. 10011110
- B. 01211110
- C. 000100000100
- D. 001000001000 Discuss
- 6. Convert each of the following signed binary numbers (two's-complement) to a signed decimal number.
00000101 11111100 11111000
Options- A. ?5 +4 +8
- B. +5 ?4 ?8
- C. ?5 +252 +248
- D. +5 ?252 ?248 Discuss
- 7. Subtract the following binary numbers.
0101 1000 1010 0011 1101 1110 ?0010 0011 ?0011 1000 ?0101 0111
Options- A. 0011 0100 0110 1010 1000 0110
- B. 0011 0101 0110 1011 1000 0111
- C. 0011 0101 0110 1010 1000 0111
- D. 0011 0101 0110 1010 1000 0110 Discuss
- 8. The 2's-complement system is to be used to add the signed binary numbers 11110010 and 11110011. Determine, in decimal, the sign and value of each number and their sum.
Options- A. ?113 and ?114, ?227
- B. ?14 and ?13, ?27
- C. ?11 and ?16, ?27
- D. ?27 and ?13, ?40 Discuss
- 9. Find the 2's complement of ?1101102.
Options- A. 1101002
- B. 1010102
- C. 0010012
- D. 0010102 Discuss
- 10. The carry propagation delay in full-adder circuits:
Options- A. is normally not a consideration because the delays are usually in the nanosecond range.
- B. decreases in a direct ratio to the total number of FA stages.
- C. is cumulative for each stage and limits the speed at which arithmetic operations are performed.
- D. increases in a direct ratio to the total number of FA stages but is not a factor in limiting the speed of arithmetic operations. Discuss
Digital Arithmetic Operations and Circuits problems
Search Results
Correct Answer: 00010000BCD
Correct Answer: ?14 and ?13, ?27
Correct Answer: inverting the B inputs.
Correct Answer: 0111
Correct Answer: 000100000100
Correct Answer: +5 ?4 ?8
Correct Answer: 0011 0101 0110 1011 1000 0111
Correct Answer: ?14 and ?13, ?27
Correct Answer: 0010102
Correct Answer: is cumulative for each stage and limits the speed at which arithmetic operations are performed.
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