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Combinational Logic Analysis
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Question
A 4-variable AND-OR circuit produces a 0 at its Y output. Which combination of inputs is correct?
Options
A. A = 0, B = 0, C = 1, D = 1
B. A = 1, B = 1, C = 0, D = 0
C. A = 1, B = 1, C = 1, D = 1
D. A = 1, B = 0, C = 1, D = 0
Correct Answer
A = 1, B = 0, C = 1, D = 0
More questions
1. On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________.
Options
A. the clock pulse is LOW
B. the clock pulse is HIGH
C. the clock pulse transitions from LOW to HIGH
D. the clock pulse transitions from HIGH to LOW
Show Answer
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Discuss
Correct Answer: the clock pulse transitions from LOW to HIGH
2. The inputs/outputs of an analog multiplexer/demultiplexer are:
Options
A. bidirectional
B. unidirectional
C. even parity
D. binary-coded decimal
Show Answer
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Discuss
Correct Answer: bidirectional
3. The hexadecimal numbering system uses base 15.
Options
A. True
B. False
Show Answer
Scratch Pad
Discuss
Correct Answer: False
4. The output voltage or current of a digital-to-analog converter is truly an analog signal.
Options
A. True
B. False
Show Answer
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Discuss
Correct Answer: False
5. Shift registers are used to store and transfer data.
Options
A. True
B. False
Show Answer
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Correct Answer: True
6. To reduce the number of pins on high-capacity DRAM chips, address ________ is used so that a single pin can accommodate two different address bits.
Options
A. conversion
B. programming
C. multiplexing
D. firmware
Show Answer
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Discuss
Correct Answer: multiplexing
7. The ________ number system has a base of sixteen.
Options
A. Johnson
B. hexadecimal
C. binary
D. octal
Show Answer
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Discuss
Correct Answer: hexadecimal
8. Using the CPLD design environment, we can simulate any combinations of inputs and observe the resulting output to check for proper circuit operation.
Options
A. True
B. False
Show Answer
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Discuss
Correct Answer: True
9. In a parity generator circuit, an error is signaled on an error indicator.
Options
A. True
B. False
Show Answer
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Discuss
Correct Answer: False
10. The gated
S-R
flip-flop is asynchronous.
Options
A. True
B. False
Show Answer
Scratch Pad
Discuss
Correct Answer: False
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