logo

CuriousTab

CuriousTab

Discussion


Home Electronics Field Effect Transistors (FET) Comments

  • Question
  • Which JFET configuration would connect a high-resistance signal source to a low-resistance load?


  • Options
  • A. source follower
  • B. common-source
  • C. common-drain
  • D. common-gate

  • Correct Answer
  • source follower 


  • Field Effect Transistors (FET) problems


    Search Results


    • 1. When applied input voltage varies the resistance of a channel, the result is called:

    • Options
    • A. saturization
    • B. polarization
    • C. cutoff
    • D. field effect
    • Discuss
    • 2. When VGS = 0 V, a JFET is:

    • Options
    • A. saturated
    • B. an analog device
    • C. an open switch
    • D. cut off
    • Discuss
    • 3. The type of bias most often used with E-MOSFET circuits is:

    • Options
    • A. constant current
    • B. drain-feedback
    • C. voltage-divider
    • D. zero biasing
    • Discuss
    • 4. Using voltage-divider biasing, what is the voltage at the gate VGS?


    • Options
    • A. 5.2 V
    • B. 4.2 V
    • C. 3.2 V
    • D. 2.2 V
    • Discuss
    • 5. When not in use, MOSFET pins are kept at the same potential through the use of:

    • Options
    • A. shipping foil
    • B. nonconductive foam
    • C. conductive foam
    • D. a wrist strap
    • Discuss
    • 6. What is the transconductance of an FET when △ID = 1 mA and △VGS = 1 V?

    • Options
    • A. 1 kS
    • B. 1 mS
    • C. 1 kΩ
    • D. 1 mΩ
    • Discuss
    • 7. In the constant-current region, how will the IDS change in an n-channel JFET?

    • Options
    • A. As VGS decreases ID decreases.
    • B. As VGS increases ID increases.
    • C. As VGS decreases ID remains constant.
    • D. As VGS increases ID remains constant.
    • Discuss
    • 8. When an input signal reduces the channel size, the process is called:

    • Options
    • A. enhancement
    • B. substrate connecting
    • C. gate charge
    • D. depletion
    • Discuss
    • 9. The overall input capacitance of a dual-gate D-MOSFET is lower because the devices are usually connected:

    • Options
    • A. in parallel
    • B. with separate insulation
    • C. with separate inputs
    • D. in series
    • Discuss
    • 10. In an n-channel JFET, what will happen at the pinch-off voltage?

    • Options
    • A. the value of VDS at which further increases in VDS will cause no further increase in ID
    • B. the value of VGS at which further decreases in VGS will cause no further increases in ID
    • C. the value of VDG at which further decreases in VDG will cause no further increases in ID
    • D. the value of VDS at which further increases in VGS will cause no further increases in ID
    • Discuss


    Comments

    There are no comments.

Enter a new Comment