Curioustab
Aptitude
General Knowledge
Verbal Reasoning
Computer Science
Interview
Aptitude
General Knowledge
Verbal Reasoning
Computer Science
Interview
Home
»
Digital Electronics
»
Integrated Circuit Technologies
Which factor does not affect CMOS loading?
Charging time associated with the output resistance of the driving gate
Discharging time associated with the output resistance of the driving gate
Output capacitance of the load gates
Input capacitance of the load gates
Correct Answer:
Output capacitance of the load gates
← Previous Question
Next Question→
More Questions from
Integrated Circuit Technologies
A certain gate draws 1.8 µA when its output is HIGH and 3.3 µA when its output is LOW. VCC is 5 V and the gate is operated on a 50% duty cycle. What is the average power dissipation (PD)?
One output structure of a TTL gate is often referred to as a ________.
The nominal value of the dc supply voltage for TTL and CMOS is ________.
If ICCH is specified as 1.1 mA when VCC is 5 V and if the gate is in a static (noncharging) HIGH output state, the power dissipation (PD) of the gate is ________.
Which is not a precaution for handling CMOS?
Unused TTL inputs should be tied LOW.
There are four different logic level ranges for TTL and CMOS: VIL, VIH, VOL, and VOH.
ECL IC technology is faster than TTL technology.
The speed-power product provides a basis for the comparison of logic circuits when power dissipation and propagation delay are important considerations in the selection of the type of logic to be used.
A pull-down resistor must be used with open-collector TTL circuits.
Discussion & Comments
No comments yet. Be the first to comment!
Name:
Comment:
Post Comment
Join Discussion
Discussion & Comments