Question 1

Identify the ADC architecture — what type is the ADC0804? The classic ADC0804 (8-bit, microprocessor-compatible ADC) belongs to which analog-to-digital conversion architecture?

Accepted Answer

Introduction / Context: The ADC0804 is a well-known 8-bit ADC used in early microprocessor systems. Recognizing its architecture helps predict speed, interface timing, and use cases. Successive-approximation (SAR) converters like ADC0804 offer deterministic, moderate-speed conversions with simple parallel interfaces, making them popular in education and embedded designs. Given Data / Assumptions: ADC0804 resolution: 8 bits, microprocessor-friendly signals (WR, INTR, CS). Typical conversion times on the order of tens to hundreds of microseconds (with an external clock). No massive comparator array as in flash ADCs. Concept / Approach: SAR ADCs perform a binary search using an internal DAC and comparator. The ADC0804 cycles through bit trials from MSB to LSB, requiring a fixed number of steps. This matches the datasheet's timing diagrams and WR/INTR handshake. Single/dual-slope parts are common in instruments but have different timing behavior, and digital-ramp (counter-type) ADCs would require variable-time counting to the code value, which the ADC0804 does not do. Step-by-Step Solution: Check interface pins: SAR-style start (WR) and end-of-conversion (INTR) are present.Review timing: fixed number of comparator decisions per conversion.No evidence of multi-comparator flash array.Conclude: ADC0804 is a SAR ADC. Verification / Alternative check: Manufacturer datasheets explicitly label ADC0804 as a successive-approximation ADC with an internal DAC and comparator. Conversion time scales with the internal clock but not with input level. Why Other Options Are Wrong: Single/dual-slope: do not match the interface and timing of ADC0804. Digital ramp: would have input-dependent conversion time and different control logic. Flash: would require 2^8 − 1 comparators and yield much higher speed. Common Pitfalls: Confusing ADC0804 (SAR) with integrating ADCs used in multimeters (dual-slope). Final Answer: successive-approximation analog-to-digital converter

Question 2

R–2R ladder DAC (4-bit) — how many distinct resistor values are required? A 4-bit R–2R ladder digital-to-analog converter is built using only replicated values. How many different resistor values are used in the ladder network?

Accepted Answer

Introduction / Context: The R–2R ladder is a highly practical DAC topology because it uses only two resistor values, regardless of resolution. This greatly simplifies matching and scaling compared with binary-weighted DACs that require precise powers-of-two resistor ratios. Understanding this property explains why R–2R ladders are common in integrated DACs and lab circuits alike. Given Data / Assumptions: We consider a standard R–2R ladder DAC for 4 bits. Ideal resistors are perfectly matched. Switches connect each bit node either to reference or ground. Concept / Approach: In an R–2R ladder, the entire network is formed by repeating segments that contain only R and 2R. Each bit adds another rung of the ladder with the same two values, ensuring that the Thevenin equivalent seen by each bit is properly scaled. The number of bits changes the number of components but never the number of distinct values required. Step-by-Step Solution: Identify ladder elements → they alternate between R and 2R.Count unique values → only two (R and 2R).Resolution (4-bit here) adds rungs but does not add new values.Therefore, the answer is two resistor values. Verification / Alternative check: Textbook schematics confirm that any N-bit R–2R DAC repeats the same two values. SPICE simulations with R = 10 kΩ and 2R = 20 kΩ demonstrate the expected binary-weighted outputs for all 4-bit codes. Why Other Options Are Wrong: One value: impossible, as the ladder requires both R and 2R. Three/four values: unnecessary—would defeat the ladder’s simplicity. “Depends on bits”: incorrect; the beauty of the ladder is independence from N. Common Pitfalls: Confusing R–2R with binary-weighted DACs that need R, 2R, 4R, 8R, etc. Final Answer: two resistor values

Question 3

Terminology — what do we call processing an analog signal in the digital domain? Choose the correct term for the manipulation, analysis, and transformation of signals after converting them to numeric form and operating on them with algorithms.

Accepted Answer

Introduction / Context: Once an analog signal is sampled and quantized by an ADC, subsequent operations—filtering, detection, compression, spectral analysis—are performed numerically. The umbrella term for these algorithmic operations executed by processors, DSP cores, or FPGAs is Digital Signal Processing (DSP). Distinguishing DSP from conversion steps is foundational for system architecture. Given Data / Assumptions: Analog signals are first acquired via sensors and ADCs. Digital hardware or software performs computations on sampled data. Outputs may remain digital or be reconverted to analog via DACs. Concept / Approach: DSP includes time- and frequency-domain operations such as FIR/IIR filtering, FFT-based spectral estimation, adaptive filtering, and modulation/demodulation in software-defined radios. The key is that the manipulation happens numerically, not by analog components. ADC and DAC are conversion interfaces, not the manipulation itself, while “signal filtering” without context could be analog or digital. Step-by-Step Solution: Acquire analog → ADC → produce sampled numeric sequence.Apply algorithms (filters, transforms, detectors) in the digital domain.Optionally output via DAC or store/transmit digitally.This pipeline defines Digital Signal Processing. Verification / Alternative check: Standard textbooks define DSP as the analysis and manipulation of signals using digital techniques, distinct from the conversion steps themselves. Why Other Options Are Wrong: Analog-to-digital conversion: the front-end conversion, not the manipulation. Digital-to-analog conversion: output interface, not processing. Signal filtering: ambiguous; could be analog filtering as well. Amplitude modulation: a specific analog/digital communications technique, not the general term. Common Pitfalls: Equating “digital filter” with ADC; the filter is the processing after conversion. Final Answer: Digital signal processing

Question 4

Applications — where is the dual-slope ADC most widely used? Select the instrument class in which the dual-slope (integrating) analog-to-digital converter is extensively employed due to its noise rejection and accuracy characteristics.

Accepted Answer

Introduction / Context: Dual-slope (integrating) ADCs are renowned for excellent rejection of line-frequency interference and for stable, accurate measurements over modest speeds. These traits make them ideal for instrumentation where precision outweighs throughput. Identifying their common application helps match ADC type to system requirements. Given Data / Assumptions: Line-frequency noise (50/60 Hz) is a common contaminant in bench measurements. Measurement intervals can be synchronized to reject such interference. Throughput needs are low (few readings per second). Concept / Approach: In a dual-slope ADC, the input is integrated for a fixed time, then a reference of opposite polarity is integrated until the integrator output returns to zero. The time of the second phase is proportional to the input voltage. Averaging during integration inherently filters noise, especially if the fixed interval equals an integer number of line cycles. Digital voltmeters traditionally adopt this approach to maximize accuracy and noise immunity at low cost. Step-by-Step Solution: Map requirements: precision and noise rejection → dual-slope architecture.Identify instrument class with such needs → DVMs and multimeters.Other instruments (function generators, counters) do not prioritize integrating conversion.Therefore, the best match is digital voltmeters. Verification / Alternative check: Service manuals and block diagrams of classic bench DVMs show integrating ADCs precisely for their line interference rejection and stable calibration behavior. Why Other Options Are Wrong: Function generators: are signal sources, not precision measurement ADC users. Frequency counters: count edges with time bases; ADCs are tangential. All of the above: overly broad and incorrect. Audio DACs: unrelated; this is about ADCs, not DACs. Common Pitfalls: Confusing “integrating ADC” with digital filtering; the integrator is analog and precedes digitization. Final Answer: digital voltmeters

Question 5

Troubleshooting DACs — which performance characteristics are evaluated? When verifying a digital-to-analog converter (DAC), which of the following characteristics might be checked to assess linearity and gain/offset behavior?

Accepted Answer

Introduction / Context: Diagnosing DAC issues requires more than a quick output check. Linearity metrics such as differential nonlinearity (DNL), integral nonlinearity (INL), and monotonicity, along with gain and offset errors, determine how faithfully digital codes translate into analog levels. A systematic evaluation helps separate device faults from reference or load problems. Given Data / Assumptions: Nonmonotonicity refers to outputs that decrease for an increasing code or vice versa. DNL measures step-size deviation between adjacent codes. “Low and high gain” here summarizes gain and offset errors (slope and intercept). Concept / Approach: To test a DAC, sweep codes across the range and measure the output with a calibrated DMM or ADC. Compute step sizes to estimate DNL, fit a line to all points to extract gain (slope) and offset (intercept), and check for monotonic behavior. Excessive DNL (> 1 LSB) can cause nonmonotonicity; significant gain/offset error skews absolute accuracy even when linearity is acceptable. Step-by-Step Solution: Apply a stable reference and proper load within compliance limits.Sweep digital input codes and record analog output.Compute consecutive code differences → DNL estimation.Fit output vs. code → gain and offset error.Inspect monotonicity → ensure strictly increasing/decreasing as expected. Verification / Alternative check: Compare measured DNL/INL with datasheet limits. Use histogram or code-density tests to reveal hidden glitches or missing codes. Why Other Options Are Wrong: Any single metric alone can miss faults; comprehensive testing includes all listed characteristics. “Only output compliance voltage” is a boundary condition, not a linearity metric. Common Pitfalls: Ignoring reference stability and load impedance; both can masquerade as DAC faults. Final Answer: all of the above

Question 6

The flash method of analog-to-digital conversion uses comparators that compare reference voltages with the analog input voltage.

Accepted Answer

True

Question 7

Digital signal processing must be at least half as fast as the incoming signal to be processed.

Accepted Answer

False

Question 8

Digital filtering is faster than analog filtering.

Accepted Answer

False

Question 9

The flash converter is the fastest analog-to-digital conversion method.

Accepted Answer

True

Question 10

Offset is the characteristic of a DAC defined by the absence of any incorrect step reversals.

Accepted Answer

False

Question 11

In a binary-weighted-input digital-to-analog converter, the values of the input resistors are chosen to be proportional to the binary weights of the corresponding input bits.

Accepted Answer

True

Question 12

Successive-approximation is perhaps the most widely used method of A/D conversion.

Accepted Answer

True

Question 13

Incorrect codes are a form of output error for a DAC.

Accepted Answer

False

Question 14

Digital signal processors must be programmed to perform specific tasks.

Accepted Answer

True

Question 15

The ADC0804 is an example of a successive-approximation ADC.

Accepted Answer

True

Question 16

The principal advantage of the three-wire handshake on the GPIB is that it ________.

Accepted Answer

allows fast and slow listeners on the same bus

Question 17

An offset error in a DAC will show up as an incorrect analog output ________.

Accepted Answer

for all inputs

Question 18

Assume that in a certain 4-bit weighted ladder DAC, the input representing the most significant bit is applied to a 20 kΩ resistor. What is the size of the resistor that represents the least significant bit?

Accepted Answer

160 kΩ

Question 19

A standard logic device can be connected on a bus system as an open-collector logic device by connecting each output to a ________.

Accepted Answer

discrete transistor

Question 20

Of the methods listed, the fastest A/D conversion is done by a ________.

Accepted Answer

successive-approximation converter

Digital Signal Processing Questions