Curioustab
Aptitude
General Knowledge
Verbal Reasoning
Computer Science
Interview
Aptitude
General Knowledge
Verbal Reasoning
Computer Science
Interview
Home
»
Digital Electronics
»
Combinational Logic Circuits
In VHDL, data can be each of the following types except ________.
BIT
BIT_VECTOR
STD_LOGIC
STD_VECTOR
Correct Answer:
STD_VECTOR
← Previous Question
Next Question→
More Questions from
Combinational Logic Circuits
A 4-bit adder has the following inputs: C0 = 0, A1 = 0, A2 = 1, A3 = 0, A4 = 1, B1 = 0, B2 = 1, B3 = 1, B4 = 1. The output will be ________.
In an odd-parity system, the data that will produce a parity bit = 1 is ________.
Parity generators and checkers use ________ gates.
When an open occurs on the input of a TTL device, the output will ________.
A half-adder does not have ________.
Occasionally, a particular logic expression will be of no consequence in the operation of a circuit, such as in a BCD-to-decimal converter. These result in ________ terms in the K-map and can be treated as either ________ or ________, in order to ________ the resulting term.
The equation ________ cannot be further simplified.
The Boolean equation ________ results from this Karnaugh map.
Two 4-bit comparators are cascaded to form an 8-bit comparator. The cascading inputs of the most significant 4 bits should be connected ________.
The AND-OR-INVERT gates are designed to simplify implementation of ________.
Discussion & Comments
No comments yet. Be the first to comment!
Name:
Comment:
Post Comment
Join Discussion
Discussion & Comments