Difficulty: Easy
Correct Answer: Incorrect
Explanation:
Introduction / Context:
Biasing methods differ for depletion-mode and enhancement-mode MOSFETs. Understanding whether a device conducts at zero gate-source voltage is key for low-power analog stages and simple current sources.
Given Data / Assumptions:
Concept / Approach:
A D-MOSFET has a physically present channel at V_GS = 0, so it naturally conducts without gate bias. Applying appropriate V_GS of the correct polarity reduces channel carriers (depletes) to reduce I_D; reversing polarity can enhance conduction. Therefore, zero-bias is not only possible but common in simple D-MOSFET applications.
Step-by-Step Solution:
Verification / Alternative check:
Datasheets specify I_DSS (drain current at V_GS = 0), confirming valid zero-bias operation for D-MOSFETs.
Why Other Options Are Wrong:
Correct: Conflicts with the presence of an I_DSS spec.
Only true for n-channel / only true at very low temperatures: Device polarity and temperature change magnitudes, not the fundamental ability to conduct at V_GS = 0.
Common Pitfalls:
Mixing up D-MOSFET and E-MOSFET behavior. Assuming V_GS = 0 always turns a MOSFET off, which is only true for enhancement-mode types.
Final Answer:
Incorrect
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