Computer architecture – memory read cycle During a memory read operation, the central processing unit (CPU) obtains information from the addressed memory location. What exactly does the CPU fetch in this read cycle?

Introduction / Context:
In basic computer architecture, every memory transaction is either a read or a write. Understanding what the CPU fetches during a memory read cycle clarifies the roles of address buses, data buses, and control lines and helps learners distinguish between instruction fetches and general data accesses.

Given Data / Assumptions:

• The CPU issues a specific address on the address bus.
• The memory subsystem decodes this address and, when Read is asserted, places the contents of that address on the data bus.
• Whether the content represents an instruction opcode or user data depends on program flow, but electrically it is still data returned from memory.

Concept / Approach:
A memory read cycle transfers bits from memory to the CPU. The CPU provides the address; the memory provides the contents. The control line (often labeled RD or MEMR) indicates the direction of transfer. An instruction fetch is just a special case of a memory read where the addressed location holds an opcode.

Step-by-Step Solution:

Verification / Alternative check:
Textbooks and timing diagrams show that during reads, data moves from memory to CPU; during writes, data moves from CPU to memory. The only thing memory returns is the stored content (data).

Why Other Options Are Wrong:
“a program instruction” is a type of data; it does not change the mechanism. “an address” is driven by the CPU to memory, not fetched from it. “all of the above” is inaccurate because the address is not fetched from memory during a read.

Common Pitfalls:
Confusing instruction fetch with a different bus operation; assuming addresses come from memory rather than from the CPU or a DMA master.

Final Answer:
data