Virtual memory basics: What is the role of a page-map table (page table) in a paged virtual memory system?

Introduction / Context:
Paged virtual memory lets processes use contiguous logical addresses even when their physical pages are scattered in RAM. The hardware and OS cooperate using a page table to translate virtual addresses to physical addresses at runtime.

Given Data / Assumptions:

• Virtual addresses are divided into page number and offset.
• Physical memory is divided into frames of the same size as pages.
• A data structure maps page numbers to frame numbers plus status bits.

Concept / Approach:

The page-map table (page table) holds entries that pair each virtual page number with a physical frame number and flags (valid, dirty, referenced, protection). The memory management unit (MMU) consults the page table (often via a TLB cache) to translate virtual addresses on the fly. It is neither a mere “data file” nor a “directory” in the filesystem sense.

Step-by-Step Solution:

Verification / Alternative check:

Hardware manuals and OS texts specify MMU translation via page tables and TLBs; exceptions occur on invalid entries, triggering page faults.

Why Other Options Are Wrong:

• A data file / A directory: These are storage abstractions, not memory-translation structures.
• All of the above: False because only address translation is accurate.
• None of the above: Incorrect because address translation is correct.

Common Pitfalls:

Confusing page tables with filesystem directories; overlooking protection bits and their role (e.g., read/write/execute) during translation.

Final Answer:

Used for address translation