Among common flip-flop designs, which configuration is inherently free from the race-around problem under edge-triggered operation?

Introduction / Context:
The race-around problem occurs in level-triggered JK configurations when both inputs are high and the clock level remains enabled, causing the output to toggle rapidly within the same clock interval. A classic solution is master–slave staging or edge-triggering, which blocks multiple toggles during a single clock event.

Given Data / Assumptions:

• We consider standard synchronous flip-flop types.
• Clocking philosophy: level vs edge triggering.
• Goal: identify a design that avoids race-around without additional constraints on pulse width.

Concept / Approach:

The master–slave JK flip-flop uses two latches in series: the master captures input on one clock level, and the slave updates output on the opposite level. This staging ensures that, even if J = K = 1, only a single toggle occurs per clock pulse because the slave does not see the master updating continuously during the same phase.

Step-by-Step Solution:

Verification / Alternative check:

Edge-triggered JK or T implementations also avoid race-around by design; master–slave is the canonical level-based method to enforce single action per clock.

Why Other Options Are Wrong:

Plain T and SR implementations can exhibit hazards or race behavior depending on clock width and input conditions. Hence they are not inherently free of race-around.

Common Pitfalls:

Assuming any JK flip-flop is safe without considering clocking style, or forgetting that master–slave specifically addresses the level-triggered hazard.

Final Answer:

master slave JK flip-flop