A Complex Programmable Logic Device (CPLD) integrates multiple PLD-like logic blocks. These blocks are tied together internally by which architectural resource?

Introduction / Context:
CPLDs scale up the concept of small PLDs by combining several logic macrocells or PLD blocks on one chip. Understanding how these blocks interconnect is crucial to grasping device architecture, timing, and routing limitations.

Given Data / Assumptions:

• CPLD comprises multiple logic blocks.
• Need to identify the internal interconnect fabric that links blocks.
• Conceptual architecture, not vendor-specific minutiae.

Concept / Approach:
CPLDs use a predictable, coarse-grained architecture where several PLD-type function blocks are connected via a global interconnection matrix (or switch matrix). This matrix provides configurable routing paths among macrocells and I/O pins, enabling designers to map logic across blocks while maintaining deterministic timing compared with many FPGAs.

Step-by-Step Solution:
1) Identify components: logic blocks (macrocells) and routing fabric.2) Recall that CPLDs feature a centralized, often hierarchical, interconnect network.3) The correct architectural term is a global interconnection matrix (switch matrix).4) Therefore, option (c) best describes the CPLD linkage.

Verification / Alternative check:
Vendor block diagrams (generic) show macrocells connected through global arrays or switch matrices, which is consistent across families.

Why Other Options Are Wrong:
Field-programmable switches: too generic; the organized fabric is the matrix.

AND/OR arrays: these live inside blocks, not the global routing layer.

Language compiler: software tool, not on-chip hardware.

External crossbar: routing resides on-chip, not externally.

Common Pitfalls:
Confusing internal macrocell logic (product terms) with the top-level routing fabric. Keep block-internal logic distinct from inter-block connectivity.

Final Answer:
a global interconnection matrix