Difficulty: Easy
Correct Answer: Correct
Explanation:
Introduction / Context:Different logic families (CMOS, TTL, ECL, etc.) exhibit distinct power behaviors. This question probes recognition of CMOS power advantages in typical operating regimes.
Given Data / Assumptions:
Concept / Approach:Static CMOS consumes very little static power because complementary transistors ideally do not both conduct in steady states. Dynamic power is roughly proportional to C * V^2 * f. Compared to TTL or ECL at similar V and f, CMOS is generally lower in power.
Step-by-Step Solution:
Step 1: Recall the CMOS static power advantage.Step 2: Note dynamic power scales with switching activity, but is still typically lower than bipolar families at like-for-like conditions.Step 3: Conclude the statement is correct.Verification / Alternative check:Datasheet comparisons (HC/HCX vs. LS-TTL vs. ECL) show CMOS families with lower typical supply current in steady state.
Why Other Options Are Wrong:
Incorrect: Conflicts with widely observed datasheet values.Only true at high frequency: High f increases dynamic losses; claim is not limited to high f.Only true for bipolar families: Statement is about CMOS vs. others; bipolar families are typically higher power.Insufficient information: Standard comparison suffices.Common Pitfalls:Overlooking dynamic power and assuming it negates CMOS advantages; it does not for typical use.
Final Answer:Correct
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