Enable gating with a fixed-period clock A clock with period 1 µs is applied to an enable gate. If exactly six clock pulses must appear at the output, how long must the enable input remain active?

Introduction / Context:
Enable gating is common in digital timing design, where a control line allows a subset of clock pulses to pass to counters or state machines. Understanding the relationship between clock period, desired pulse count, and enable width is foundational.

Given Data / Assumptions:

• Clock period T = 1 µs.
• We need exactly N = 6 pulses at the output.
• Gate is ideal and passes pulses only while enable is active.

Concept / Approach:
The number of whole pulses that can pass equals the active time divided by the clock period. For an integer number of pulses with clean edges and no synchronization latency, the active time should be N * T.

Step-by-Step Solution:
Compute total time required: t_active = N * T.Substitute N = 6 and T = 1 µs.t_active = 6 * 1 µs = 6 µs.Therefore, enable must be asserted for 6 µs.

Verification / Alternative check:
Observe a timing diagram: with enable high across six consecutive rising edges, six pulses get through. If enabled for 3 µs, only three pulses pass; if for 12 µs, twelve pulses would pass.

Why Other Options Are Wrong:
0 µs: no pulses can pass.3 µs: only 3 pulses at 1 µs period.12 µs: would pass 12 pulses, not 6.

Common Pitfalls:
Forgetting that the count depends on whole periods; edge alignment and gate propagation must be considered in real hardware to avoid off-by-one counts.

Final Answer:
Enable must be active for 6 µs.