Introduction / Context:
Application-Specific Integrated Circuits (ASICs) encompass multiple implementation styles. Understanding the four classic categories helps engineers weigh NRE cost, performance, time-to-market, and unit cost.
Given Data / Assumptions:
- Common categories include PLDs (programmable logic devices), gate arrays (semi-custom with prefabricated transistors), and standard cells (cell libraries placed and routed).
- A fourth category reflects maximum customization at the transistor/layout level.
- Terminology focuses on implementation style rather than vendor-specific branding.
Concept / Approach:
The missing category is “full custom,” where every transistor and interconnect can be hand-crafted for optimal speed, power, and area. This approach has the highest NRE and longest development cycle but enables peak performance and density.
Step-by-Step Solution:
List known three → PLDs, gate arrays, standard cells.Identify the top-customization category → full custom ASIC.Therefore, the fourth category is “full custom.”
Verification / Alternative check:
ASIC design textbooks consistently present these four tracks.
Why Other Options Are Wrong:
HCPLDs: Not a standard ASIC category; CPLD is a PLD subclass, not separate in this quartet.GAL: A specific SPLD type, not an ASIC category.FPLDs: General term for programmable logic (e.g., FPGA/CPLD) already covered under PLDs.
Common Pitfalls:
Confusing device families (e.g., GAL) with implementation categories.Thinking gate arrays include full-custom; they do not—they are semi-custom.
Final Answer:
full custom
Discussion & Comments