Which x86 microprocessor family used multiplexed address/data lines on its external bus? Choose the processor that famously time-shared AD lines (address during T1, data during later bus states) to reduce pin count.

Introduction / Context:
To minimize package pins, early microprocessors often multiplexed address and data on the same physical lines and used a signal such as ALE to latch the address externally. Recognizing which generation used this technique helps when reading legacy schematics and timing diagrams.

Given Data / Assumptions:

• Multiplexed lines labeled AD0–AD15 on 8086/8088.
• ALE (Address Latch Enable) demultiplexes the address into external latches.

Concept / Approach:
The 8086/8088 bus cycles place address on the AD lines during the first state (T1) and data on those same lines during subsequent states (T2–T4). Later processors increased pin counts and bus widths, reducing the need for such multiplexing at the package level in typical implementations.

Step-by-Step Solution:

Verification / Alternative check:
Original Intel hardware manuals show bus timing with multiplexed address/data phases and ALE strobes.

Why Other Options Are Wrong:

• 80286/80386/Pentium/Core: later designs typically expose separate address and data buses or very different bus protocols.

Common Pitfalls:

• Assuming all x86 generations share identical external bus wiring; many details changed substantially across generations.

Final Answer:
8086/8088