A waveform can be enabled or disabled by both AND and OR gates.

More Questions from Logic Gates

• A NAND gate output is LOW only if all the inputs are HIGH.
• A truth table illustrates how the input level of a gate responds to all the possible output level combinations.
• A NOR gate output is LOW if any of its inputs is LOW.
• The gates in this figure are implemented using TTL logic. If the output of the inverter is open, and you apply logic pulses to point B, the output of the AND gate will be ________.
• The gates in this figure are implemented using TTL logic. If the output of the inverter has an internal open circuit, what voltage would you expect to measure at the inverter's output?
• When does the output of a NOR gate = 0?
• The gates in this figure are implemented using TTL logic. If the input of the inverter is open, and you apply logic pulses to point B, the output of the AND gate will be ________.
• When does the output of a NAND gate = 1?
• A major advantage of ECL logic over TTL and CMOS is ________.
• The number of input combinations for a 4-input gate is ________.

Discussion & Comments