Two’s-complement subtraction – which core operation does the hardware actually perform to realize A − B?

Introduction / Context:
Efficient ALU design avoids separate subtractors by leveraging two’s-complement properties. Subtraction is “free” once addition is available, which simplifies datapaths and timing closure. Understanding this equivalence helps when writing synthesizable HDL and when reading synthesis reports.

Given Data / Assumptions:

• Operands A and B are fixed-width two’s-complement numbers.
• We want A − B.
• We can control inversion of B and the initial carry-in of an adder.

Concept / Approach:
Compute A − B as A + (NOT(B) + 1). The adder accepts B after bitwise inversion while the carry-in is preset to 1, effectively adding the two’s complement of B. The same ripple-carry or carry-lookahead adder thus performs both addition and subtraction, reducing hardware.

Step-by-Step Solution:

Verification / Alternative check:
Example: 7 − 5 (4-bit). A=0111, B=0101. Invert B→1010; add with Cin=1: 0111 + 1010 + 1 = 1 0000 → 0000 with carry out; because of fixed width, also compute directly with two’s complement of B (1011) to get 0010 = 2, consistent when steps are tracked correctly. The key is that the hardware path is addition with controlled inversion and carry-in.

Why Other Options Are Wrong:
Dedicated borrow subtractors are unnecessary in two’s complement. Multiplication or division are unrelated. Lookup tables are not how arithmetic is generally synthesized in standard ALUs.

Common Pitfalls:
Misreading the carry and overflow flags between signed and unsigned modes; forgetting to preset Cin; or accidentally double-adding the +1.

Final Answer:
addition