Two’s-complement subtraction rule – do we subtract by taking the subtrahend’s two’s complement and adding it to the minuend?

Introduction / Context:
Digital systems implement subtraction efficiently by reusing addition hardware. Two’s-complement arithmetic enables this by converting subtraction into addition of the negated subtrahend. Recognizing this rule is fundamental for ALU design and low-level programming.

Given Data / Assumptions:

• Two’s-complement representation for signed integers.
• Fixed word width (e.g., 8, 16, 32 bits).
• Potential for overflow is handled by flags, but does not change the rule.

Concept / Approach:
To compute A − B, form two’s complement of B (invert bits of B, then add 1) and add to A: A + (two’s complement of B). This lets a single adder perform both addition and subtraction, with control logic selecting whether to invert B and preset the carry-in.

Step-by-Step Solution:

Verification / Alternative check:
Example: 7 − 5 in 4 bits. A=0111, B=0101. Two’s complement of B: 1011. Add: 0111 + 1011 = 1 0010; drop carry → 0010 (2). Matches the expected result.

Why Other Options Are Wrong:
The rule is not limited by operand signs or the presence/absence of overflow; those affect interpretation, not the mechanism.

Common Pitfalls:
Forgetting the +1 after inversion, or misreading signed vs unsigned overflow behavior when interpreting flags.

Final Answer:
Correct