Overflow conditions in 2's-complement addition: For the sum of two signed 2's-complement numbers to overflow, what must be true about the signs of the addends?

Introduction / Context:
In 2's-complement arithmetic, overflow occurs when the true mathematical result cannot be represented in the available fixed-width format. Recognizing the sign patterns that cause overflow is essential for CPU ALUs, DSP code, and safety checks in embedded systems.

Given Data / Assumptions:

• Fixed width N-bit 2's-complement representation.
• Two signed addends are added.
• Overflow flagging is based on sign behavior, not just carry out of MSB.

Concept / Approach:
Overflow in 2's complement addition happens when adding two positives yields a negative result, or adding two negatives yields a positive result. This only occurs when the two inputs share the same sign and the resulting sign differs. If the inputs have opposite signs, the sum moves toward zero and cannot overflow the representable range.

Step-by-Step Solution:

Verification / Alternative check:
Hardware rule: Overflow = carry into MSB XOR carry out of MSB. This condition evaluates true precisely in the same-sign overflow scenarios above.

Why Other Options Are Wrong:

Common Pitfalls:
Confusing carry-out with overflow; applying unsigned intuition to signed operations; ignoring fixed width truncation effects.

Final Answer:
have the same sign