Suppose you have a computional circuit between two registers driven by a clock. What will you do if the delay of the combinational circuit is greater than your clock signal?

Correct Answer: Use the concept of register-retiming divide the totla combinatorial delay in two segments such that individually the delay is less the clock period this can be done by inserting a flip-flop in the combinational path eg, clock period --- 5 ns total cominational delay ---- 7 then divide the 7ns path in two path of 4 or 3 (best resutls are obtained if delays are same for both path ie 35ns) by inserting a flip-flop in between