In first-order circuits, when do we say a steady-state condition has been reached during a DC step response?

Introduction / Context:Steady state in basic RC/RL circuits typically refers to conditions after all transients have died out. For a DC step input, energy storage elements settle to constant voltages/currents and derivatives go to zero. This question targets that definition.

Given Data / Assumptions:

• DC step input applied to a first-order circuit (e.g., charging a capacitor through a resistor).
• No leakage (unless stated), linear components, and ideal source.

Concept / Approach:During a DC step, the forced response is a constant value, and the natural response decays exponentially with time constant tau. Steady state is reached as t → ∞, when the exponential term decays to zero. In a simple RC charge with a step from 0 to V_in, the capacitor voltage tends to V_in; thus output equals input (for the node across the capacitor) in steady state.

Step-by-Step Solution:

Verification / Alternative check:After ~5 tau, first-order responses are within ~1% of final value, commonly used as a practical steady-state criterion. Simulation or lab measurement confirms negligible change beyond this horizon.

Why Other Options Are Wrong:

• Average value: Relevant to periodic waveforms, not to a DC step.
• 63% of input: That is the one-time-constant point, not steady state.
• Effective (rms) value: Pertains to AC; a DC final value equals the DC amplitude.

Common Pitfalls:

• Confusing the 63% milestone with completion of the transient.
• Mixing AC metrics (rms, average over a cycle) with DC step responses.

Final Answer:When the output voltage reaches the input voltage (for a DC step)