In computer architecture and pipeline design, a data hazard occurs under which of the following conditions during instruction execution?

Introduction / Context:
This question belongs to the topic of instruction pipelining in computer architecture. Pipelining improves performance by overlapping the execution of multiple instructions, but it also introduces hazards that can cause incorrect results if not handled properly. Data hazards are one category of such hazards and occur when instructions depend on the results of previous instructions that have not yet completed. Understanding when a data hazard occurs is crucial for designing pipeline control logic and for appreciating how modern processors maintain correctness while executing instructions in overlapping stages.

Given Data / Assumptions:

• The question asks about data hazards in computer science, specifically in the context of pipelines.
• The options mention changes in the order of read or write access to operands, performance loss, machine size, and incomplete pipelining of functional units.
• We assume a typical pipelined CPU with stages such as fetch, decode, execute, memory access, and write back.
• We also assume that operands refer to registers or memory locations used by instructions.

Concept / Approach:
A data hazard occurs when the pipeline changes the expected order of operand access, leading to read or write conflicts. For example, if an instruction needs to read a register that a previous instruction is still updating, there is a read after write dependency. If the pipeline allows the second instruction to move ahead and read the register before the first one completes its write, the second instruction might receive an old value, causing incorrect computation. This situation is a classic data hazard. Data hazards are categorized as read after write, write after read, or write after write, depending on the order of operations that causes the conflict. General performance loss or limited machine size may be side effects of many problems, but they are not the precise definition of a data hazard.

Step-by-Step Solution:
Step 1: Focus on the phrase data hazard and recall that it refers to operand dependencies in a pipeline.Step 2: Remember that data hazards arise when one instruction depends on the result of another and the pipeline changes the normal timing of reads and writes.Step 3: Examine option A, which explicitly mentions the pipeline changing the order of read or write access to operands, creating potential conflicts.Step 4: Compare this to the other options, which mention generic performance loss, machine size, or incomplete pipelining but do not mention operand access conflicts.Step 5: Conclude that option A accurately describes when a data hazard occurs in pipelined systems.

Verification / Alternative check:
Textbooks on computer architecture define data hazards as conditions where the order of read and write operations in the pipeline leads to incorrect use of data. Examples include an instruction trying to use a value that has not yet been written back to a register or memory location. Solutions such as forwarding, pipeline stalls, and register renaming are introduced specifically to handle data hazards. None of these discussions focus on physical machine size or generic performance loss as the core definition. Therefore, the precise characteristic of a data hazard is the conflict in operand access ordering, as described in option A.

Why Other Options Are Wrong:
Option B is incorrect because performance loss can be a symptom of many different issues, including hazards, but it does not define a data hazard. Option C is incorrect because machine size refers to the physical or logical scale of the system and is unrelated to operand dependency conflicts. Option D is incorrect because a functional unit not being fully pipelined may limit throughput but does not by itself cause the pipeline to read or write operands in the wrong order. Only option A, describing the pipeline changing the order of read and write access to operands, directly matches the concept of a data hazard.

Common Pitfalls:
Students sometimes confuse different types of pipeline hazards, such as control hazards from branches, structural hazards from resource conflicts, and data hazards from operand dependencies. Another pitfall is to mistake any slowdown or inefficiency for a hazard, even when the pipeline still produces correct results. It is important to remember that a hazard is about the potential for incorrect behavior unless the system takes specific steps to avoid it. For data hazards, this incorrect behavior arises when operand values are read or written at the wrong time relative to other instructions. Keeping this precise definition in mind helps differentiate data hazards from other performance related concerns.

Final Answer:
The correct answer is When the pipeline changes the normal order of read and write access to operands, causing potential conflicts.