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In an AC circuit where the input frequency is such that the resistance R is equal to the capacitive reactance XC, what is the phase relationship between the output voltage v0 and the input voltage vi?

Difficulty: Medium

Correct Answer: v0 lags vi by 45°

Explanation:


Introduction / Context:
Phase relationships in RC circuits are a fundamental concept in AC circuit analysis. When the resistance R and the capacitive reactance XC are equal, the circuit reaches a specific balance point that defines the exact phase shift between input and output voltages.


Given Data / Assumptions:

  • Series RC circuit with input sinusoidal source.
  • At the operating frequency, R = XC.
  • v0 refers to the voltage across the capacitor or across the resistor depending on the circuit definition. Standard analysis assumes v0 across the capacitor.


Concept / Approach:
Impedance of resistor: Z_R = R∠0°. Impedance of capacitor: Z_C = −jXC. When R = XC, the total impedance becomes Z_total = R − jR. The phasor angle θ = tan⁻¹(−R/R) = −45°. Therefore, the total current leads the input voltage by 45°, and the voltage across the capacitor lags the input by 45°.


Step-by-Step Solution:

Z_total = R − jR = R(1 − j).Magnitude |Z_total| = √(R² + R²) = R√2.Phase angle = tan⁻¹(−R/R) = −45°.Current I leads source voltage by 45°. Capacitor voltage v0 lags current by 90°. Therefore v0 lags vi by 45° overall.


Verification / Alternative check:

Simulation or phasor diagrams confirm that at the condition R = XC, the circuit behaves as a 45° phase lag network.


Why Other Options Are Wrong:

90° lag: true only if pure capacitor (R = 0).Leads: incorrect for a capacitive branch output.In phase: occurs only if XC = 0 (pure resistor).


Common Pitfalls:

Mixing up whether v0 is across R or C; for capacitor output, lag occurs.


Final Answer:

v0 lags vi by 45°
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