Flip-Flops and Timers Questions

• A D-type flip-flop is constructed by connecting an inverter between the Set and Clock terminals.
• When the S and the R inputs are both HIGH the output of an S-R NOR latch will be unpredictable.
• J-K flip-flops are often used as switch debouncers.
• The J-K flip-flop eliminates the RACE state when both the J and K inputs are HIGH.
• Edge-triggered flip-flops must have _________.
• The S-R, D-type, and J-K flip-flops are all examples of _________________.
• A retriggerable one-shot has a pulse width of 10 ms; 3 ms after being triggered, another trigger pulse is applied. The resulting output pulse will be _________ ms.
• An S-R NAND latch with both of its inputs LOW has an output that is _____________.
• If an input is activated by a signal transition, it is _____________.
• The toggle condition in a master-slave J-K flip-flop means that Q and will switch to their ________ state(s) at the _____________________.
• An S-R flip-flop can be triggered by ______, ______, or ________.
• Pulse-triggered flip-flops are also called _________ flip-flops.
• One example of the use of an S-R flip-flop is as a(n) _________.
• For an S-R flip-flop to be SET or RESET, the respective input must be __________.