In the classic 4-bit ALU IC 74181, arithmetic addition and subtraction operations are effectively carried out in which number system representation?

Introduction / Context:
The 74181 is a classic TTL 4-bit arithmetic logic unit that implements a variety of logic and arithmetic functions. Understanding how subtraction is realized clarifies the number representation effectively supported by the chip in typical CPU designs.

Given Data / Assumptions:

• 74181 provides arithmetic functions including A + B and A + Ā + 1 (which can represent A − B).
• Carry-in (Cn) control is available to facilitate two’s-complement subtraction.
• Outputs include sum and carry allowing ripple-carry extension across nibbles.

Concept / Approach:

Two’s-complement subtraction A − B is implemented as A + (two’s complement of B) = A + (B̄ + 1). The 74181 can complement one operand and accept a carry-in of 1, thereby performing subtraction through addition, which is the standard two’s-complement technique.

Step-by-Step Solution:

Verification / Alternative check:

Manufacturer datasheets show function tables enabling addition with complemented inputs and carry-in, confirming two’s-complement subtraction support across cascaded 74181 stages for wider word lengths.

Why Other Options Are Wrong:

• 1’s complement: Would require end-around carry handling; not how 74181 subtraction is normally configured.
• Binary (unsigned only): The same hardware supports signed arithmetic via two’s complement interpretation.
• 'none of the above' / 'excess-3': Not applicable to 74181 arithmetic modes.

Common Pitfalls:

Assuming a separate subtractor is required; misunderstanding that complement-and-add with carry-in is precisely the two’s-complement method.

Final Answer:

2's complement