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- Question
When an open occurs on the input of a CMOS gate, the output will ________.
Options- A. go LOW, because there is no current in an open circuit
- B. react as if the open input were a HIGH
- C. go HIGH, since full voltage appears across an open
- D. be unpredictable; it may go HIGH or LOW
- Correct Answer
- be unpredictable; it may go HIGH or LOW
- 1. The largest truth table that can be implemented directly with an 8-line-to-1-line MUX has ________.
Options- A. 3 rows
- B. 4 rows
- C. 8 rows
- D. 16 rows Discuss
- 2. The output of a gate has an internal short; a current tracer will ________.
Options- A. identify the defective gate
- B. show whether the gate is shorted to Vcc or ground
- C. probably not be able to locate the problem
- D. be able to identify the defective load node Discuss
- 3. One reason for using the sum-of-products form is that it can be implemented using all ________ gates without much difficulty.
Options- A. NOR
- B. NAND
- C. AND
- D. DOOR Discuss
- 4. The simplified form of
is ________.
Options- A.
- B.
- C.
- D.
Discuss
- 5. When grouping cells within a K-map, the cells must be combined in groups of ________.
Options- A. 2's
- B. 1, 2, 4, 8, etc.
- C. 4's
- D. 3's Discuss
- 6. VHDL is very strict in the way it allows us to assign and compare ________ such as signals, variables, constants, and literals.
Options- A. objects
- B. LOGIC_VECTORS
- C. designs
- D. arrays Discuss
- 7. ________ is a correct combination for an ODD-parity data transmission system.
Options- A. data = 1101 1011
parity = 1 - B. data = 1101 0010
parity = 0 - C. data = 0001 0101
parity = 1 - D. data = 1010 1111
parity = 0
Discuss
- 8. The ________ circuit produces a HIGH output whenever the two inputs are equal.
Options- A. exclusive-AND
- B. exclusive-NAND
- C. exclusive-NOR
- D. exclusive-OR Discuss
- 9. The addition of two signed numbers in the 2's complement system can cause overflow. For overflow to occur both numbers must ________.
Options- A. be positive
- B. be negative
- C. have the same sign
- D. have opposite signs Discuss
- 10. After each circuit in a subsection of a VHDL program has been ________, they can be combined and the subsection can be tested.
Options- A. designed
- B. tested
- C. engineered
- D. produced Discuss
Combinational Logic Circuits problems
Search Results
Correct Answer: 8 rows
Correct Answer: identify the defective gate
Correct Answer: NAND
Correct Answer:
Correct Answer: 1, 2, 4, 8, etc.
Correct Answer: objects
Correct Answer: data = 1101 1011
parity = 1
Correct Answer: exclusive-NOR
Correct Answer: have the same sign
Correct Answer: tested
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