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Home ‣ Digital Electronics ‣ Combinational Logic Circuits Comments
  • Question

  • When grouping cells within a K-map, the cells must be combined in groups of ________.


  • Options
  • A. 2's
  • B. 1, 2, 4, 8, etc.
  • C. 4's
  • D. 3's

  • Correct Answer
  • 1, 2, 4, 8, etc. 

    • Combinational Logic Circuits problems

    Search Results

    • 1. The ________ series of IC's are pin, function, and voltage-level compatible with the 74 series IC's.

    • Options
    • A. ALS
    • B. CMOS
    • C. HCT
    • D. 2N
      • Discuss
    • 2. The ________ circuit produces a HIGH output whenever the two inputs are unequal.

    • Options
    • A. exclusive-AND
    • B. exclusive-NOR
    • C. exclusive-OR
    • D. inexclusive-OR
      • Discuss
    • 3. A gate that could be used to compare two logic levels and provide a HIGH output if they are equal is a(n) ________.

    • Options
    • A. XOR gate
    • B. XNOR gate
    • C. NAND gate
    • D. NOR gate
      • Discuss
    • 4. For the XNOR gate truth table shown below, the values for w, x, y, and z are ____, ____, ____, and ____, respectively.


    • Options
    • A. 1, 0, 0, 1
    • B. 0, 1, 0, 1
    • C. 1, 1, 1, 0
    • D. 1, 0, 0, 0
      • Discuss
    • 5. The ________ prefix on IC's indicates a broader operating temperature range, and the devices are generally used by the military.

    • Options
    • A. 54
    • B. 2N
    • C. 74
    • D. TTL
      • Discuss
    • 6. The simplified form of is ________.

    • Options
    • A.
    • B.
    • C.
    • D.
      • Discuss
    • 7. One reason for using the sum-of-products form is that it can be implemented using all ________ gates without much difficulty.

    • Options
    • A. NOR
    • B. NAND
    • C. AND
    • D. DOOR
      • Discuss
    • 8. The output of a gate has an internal short; a current tracer will ________.

    • Options
    • A. identify the defective gate
    • B. show whether the gate is shorted to Vcc or ground
    • C. probably not be able to locate the problem
    • D. be able to identify the defective load node
      • Discuss
    • 9. The largest truth table that can be implemented directly with an 8-line-to-1-line MUX has ________.

    • Options
    • A. 3 rows
    • B. 4 rows
    • C. 8 rows
    • D. 16 rows
      • Discuss
    • 10. When an open occurs on the input of a CMOS gate, the output will ________.

    • Options
    • A. go LOW, because there is no current in an open circuit
    • B. react as if the open input were a HIGH
    • C. go HIGH, since full voltage appears across an open
    • D. be unpredictable; it may go HIGH or LOW
      • Discuss

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