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- Question
The carry propagation delay in 4-bit full-adder circuits ____________.
Options- A. is normally not a consideration because the delays are usually in the nanosecond range
- B. is cumulative for each stage and limits the speed at which arithmetic operations are performed
- C. decreases in direct ratio to the total number of full-adder stages
- D. increases in direct ratio to the total number of full-adder stages, but is not a factor in limiting the speed of arithmetic operations
- Correct Answer
- is cumulative for each stage and limits the speed at which arithmetic operations are performed
- 1. A full adder adds ____.
Options- A. two 2-bit binary numbers
- B. two 4-bit binary numbers
- C. two single bits and one carry bit
- D. two 2-bit numbers and one carry bit Discuss
- 2. The 2's complement of 1101102 is _________.
Options- A. 1101002
- B. 1010102
- C. 0010112
- D. 0010102 Discuss
- 3. The operands in an addition operation consist of the augend and the addend.
Options- A. True
- B. False Discuss
- 4. The operands in a subtraction operation are the subend and the minuend.
Options- A. True
- B. False Discuss
- 5. A full adder adds three bits, a half adder adds 1-1/2 bits.
Options- A. True
- B. False Discuss
- 6. All digital systems that perform arithmetic operations must indicate _______ and ________ for numbers.
Options- A. size, base
- B. sign, magnitude
- C. sign, base
- D. magnitude, base Discuss
- 7. An input to the mode pin of an arithmetic-logic unit (ALU) determines if the function will be _________.
Options- A. one's complemented
- B. positive or negative
- C. with or without carry
- D. arithmetic or logic Discuss
- 8. In binary number systems the sign of a number is indicated by _________.
Options- A. using a 0 (zero) bit in front of negative numbers
- B. inverting the bits if the number is negative
- C. including a sign bit along with the magnitude bits
- D. placing a negative sign in front of the number Discuss
- 9. Two 4-bit adders could be cascaded to form a(n) ___________.
Options- A. 16-bit parallel-adder circuit
- B. 8-bit parallel-adder circuit
- C. full-adder circuit
- D. arithmetic-logic unit Discuss
- 10. One advantage of using the 2's complement system to represent signed numbers is that you ___________.
Options- A. can perform subtraction by performing addition
- B. can perform addition by performing subtraction
- C. can perform division through repeated subtraction
- D. none of the above Discuss
Arithmetic Operations and Circuits problems
Search Results
Correct Answer: two single bits and one carry bit
Correct Answer: 0010102
Correct Answer: True
Correct Answer: False
Correct Answer: False
Correct Answer: sign, magnitude
Correct Answer: arithmetic or logic
Correct Answer: including a sign bit along with the magnitude bits
Correct Answer: 8-bit parallel-adder circuit
Correct Answer: can perform subtraction by performing addition
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