A full adder adds three bits, a half adder adds 1-1/2 bits. True False

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Home ‣ Electronics ‣ Arithmetic Operations and Circuits Comments

Question
A full adder adds three bits, a half adder adds 1-1/2 bits.
Options
A. True
B. False

Correct Answer

False

Arithmetic Operations and Circuits problems

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1. End around carry is an operation in 1's complement subtraction where a 1 is added to the sum of the 1's complement of both numbers.
Options
A. True
B. False

Discuss

Correct Answer: False

2. Using the two's complement number system we can add numbers with like signs and obtain the correct result.
Options
A. True
B. False

Discuss

Correct Answer: False

3. If you borrow from a position that contains a 0, you must borrow from the more significant bit that contains a 1. All 0s up to that point become 1s, and the digit last borrowed from becomes a 0.
Options
A. True
B. False

Discuss

Correct Answer: True

4. Signed binary numbers have one bit that represents the sign, with the remaining bits representing the magnitude.
Options
A. True
B. False

Discuss

Correct Answer: True

5. A technique to speed parallel addition by eliminating the delay caused by the carry bit propagation is called fast carry, or look-ahead carry.
Options
A. True
B. False

Discuss

Correct Answer: True

6. The operands in a subtraction operation are the subend and the minuend.
Options
A. True
B. False

Discuss

Correct Answer: False

7. The operands in an addition operation consist of the augend and the addend.
Options
A. True
B. False

Discuss

Correct Answer: True

8. The 2's complement of 110110₂ is _________.
Options
A. 110100₂
B. 101010₂
C. 001011₂
D. 001010₂

Discuss

Correct Answer: 001010₂

9. A full adder adds ____.
Options
A. two 2-bit binary numbers
B. two 4-bit binary numbers
C. two single bits and one carry bit
D. two 2-bit numbers and one carry bit

Discuss

Correct Answer: two single bits and one carry bit

10. The carry propagation delay in 4-bit full-adder circuits ____________.
Options
A. is normally not a consideration because the delays are usually in the nanosecond range
B. is cumulative for each stage and limits the speed at which arithmetic operations are performed
C. decreases in direct ratio to the total number of full-adder stages
D. increases in direct ratio to the total number of full-adder stages, but is not a factor in limiting the speed of arithmetic operations

Discuss

Correct Answer: is cumulative for each stage and limits the speed at which arithmetic operations are performed

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A full adder adds three bits, a half adder adds 1-1/2 bits.

Arithmetic Operations and Circuits problems

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