logo

CuriousTab

CuriousTab

Discussion

Home ‣ Electronics ‣ Arithmetic Operations and Circuits Comments
  • Question

  • A technique to speed parallel addition by eliminating the delay caused by the carry bit propagation is called fast carry, or look-ahead carry.


  • Options
  • A. True
  • B. False

  • Correct Answer
  • True 

    • Arithmetic Operations and Circuits problems

    Search Results

    • 1. Two half adders can be combined to form a full adder with no additional gates.

    • Options
    • A. True
    • B. False
      • Discuss
    • 2. For an S-R flip-flop to be SET or RESET, the respective input must be __________.

    • Options
    • A. LOW
    • B. HIGH
    • C. installed with steering diodes
    • D. in parallel with a limiting resistor
      • Discuss
    • 3. One example of the use of an S-R flip-flop is as a(n) _________.

    • Options
    • A. racer
    • B. binary storage register
    • C. astable oscillator
    • D. transition pulse generator
      • Discuss
    • 4. Pulse-triggered flip-flops are also called _________ flip-flops.

    • Options
    • A. master-slave
    • B. postponed
    • C. level
    • D. edge
      • Discuss
    • 5. An S-R flip-flop can be triggered by ______, ______, or ________.

    • Options
    • A. HIGHs, LOWs, PRESETs
    • B. edges, levels, pulses
    • C. HIGHs, LOWs, CLEARs
    • D. SETs, RESETs, HIGHs
      • Discuss
    • 6. Signed binary numbers have one bit that represents the sign, with the remaining bits representing the magnitude.

    • Options
    • A. True
    • B. False
      • Discuss
    • 7. If you borrow from a position that contains a 0, you must borrow from the more significant bit that contains a 1. All 0s up to that point become 1s, and the digit last borrowed from becomes a 0.

    • Options
    • A. True
    • B. False
      • Discuss
    • 8. Using the two's complement number system we can add numbers with like signs and obtain the correct result.

    • Options
    • A. True
    • B. False
      • Discuss
    • 9. End around carry is an operation in 1's complement subtraction where a 1 is added to the sum of the 1's complement of both numbers.

    • Options
    • A. True
    • B. False
      • Discuss
    • 10. A full adder adds three bits, a half adder adds 1-1/2 bits.

    • Options
    • A. True
    • B. False
      • Discuss

    Comments

    There are no comments.
Enter a new Comment




Aptitude

Engineering

Programming

Reasoning

Links

Copyright ©CuriousTab. All rights reserved.