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Flip-Flops and Timers
Comments
Question
Pulse-triggered flip-flops are also called _________ flip-flops.
Options
A. master-slave
B. postponed
C. level
D. edge
Correct Answer
master-slave
Flip-Flops and Timers problems
Search Results
1. An S-R flip-flop can be triggered by ______, ______, or ________.
Options
A. HIGHs, LOWs, PRESETs
B. edges, levels, pulses
C. HIGHs, LOWs, CLEARs
D. SETs, RESETs, HIGHs
Show Answer
Scratch Pad
Discuss
Correct Answer: edges, levels, pulses
2. The toggle condition in a master-slave J-K flip-flop means that Q and
will switch to their ________ state(s) at the _____________________.
Options
A. inverted, positive clock edge
B. quiescent, negative clock edge
C. opposite, active clock edge
D. reset, synchronous clock edge
Show Answer
Scratch Pad
Discuss
Correct Answer: opposite, active clock edge
3. If an input is activated by a signal transition, it is _____________.
Options
A. edge-triggered
B. toggle-triggered
C. clock-triggered
D. noise-triggered
Show Answer
Scratch Pad
Discuss
Correct Answer: edge-triggered
4. An S-R NAND latch with both of its inputs LOW has an output that is _____________.
Options
A. unpredictable
B. floating
C. HIGH
D. LOW
Show Answer
Scratch Pad
Discuss
Correct Answer: unpredictable
5. A retriggerable one-shot has a pulse width of 10 ms; 3 ms after being triggered, another trigger pulse is applied. The resulting output pulse will be _________ ms.
Options
A. 3
B. 7
C. 10
D. 13
Show Answer
Scratch Pad
Discuss
Correct Answer: 13
6. One example of the use of an S-R flip-flop is as a(n) _________.
Options
A. racer
B. binary storage register
C. astable oscillator
D. transition pulse generator
Show Answer
Scratch Pad
Discuss
Correct Answer: binary storage register
7. For an S-R flip-flop to be SET or RESET, the respective input must be __________.
Options
A. LOW
B. HIGH
C. installed with steering diodes
D. in parallel with a limiting resistor
Show Answer
Scratch Pad
Discuss
Correct Answer: HIGH
8. Two half adders can be combined to form a full adder with no additional gates.
Options
A. True
B. False
Show Answer
Scratch Pad
Discuss
Correct Answer: False
9. A technique to speed parallel addition by eliminating the delay caused by the carry bit propagation is called fast carry, or look-ahead carry.
Options
A. True
B. False
Show Answer
Scratch Pad
Discuss
Correct Answer: True
10. Signed binary numbers have one bit that represents the sign, with the remaining bits representing the magnitude.
Options
A. True
B. False
Show Answer
Scratch Pad
Discuss
Correct Answer: True
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