Discussion
Home ‣ Electronics ‣ Flip-Flops and Timers Comments
- Question
The toggle condition in a master-slave J-K flip-flop means that Q and
will switch to their ________ state(s) at the _____________________.
Options- A. inverted, positive clock edge
- B. quiescent, negative clock edge
- C. opposite, active clock edge
- D. reset, synchronous clock edge
- Correct Answer
- opposite, active clock edge
- 1. If an input is activated by a signal transition, it is _____________.
Options- A. edge-triggered
- B. toggle-triggered
- C. clock-triggered
- D. noise-triggered Discuss
- 2. An S-R NAND latch with both of its inputs LOW has an output that is _____________.
Options- A. unpredictable
- B. floating
- C. HIGH
- D. LOW Discuss
- 3. A retriggerable one-shot has a pulse width of 10 ms; 3 ms after being triggered, another trigger pulse is applied. The resulting output pulse will be _________ ms.
Options- A. 3
- B. 7
- C. 10
- D. 13 Discuss
- 4. The S-R, D-type, and J-K flip-flops are all examples of _________________.
Options- A. astable multivibrators
- B. bistable multivibrators
- C. monostable multivibrators
- D. tristable multivibrators Discuss
- 5. Edge-triggered flip-flops must have _________.
Options- A. very fast response times
- B. at least two inputs to handle rising and falling edges
- C. a positive-transition pulse generator
- D. a negative-transition pulse generator Discuss
- 6. An S-R flip-flop can be triggered by ______, ______, or ________.
Options- A. HIGHs, LOWs, PRESETs
- B. edges, levels, pulses
- C. HIGHs, LOWs, CLEARs
- D. SETs, RESETs, HIGHs Discuss
- 7. Pulse-triggered flip-flops are also called _________ flip-flops.
Options- A. master-slave
- B. postponed
- C. level
- D. edge Discuss
- 8. One example of the use of an S-R flip-flop is as a(n) _________.
Options- A. racer
- B. binary storage register
- C. astable oscillator
- D. transition pulse generator Discuss
- 9. For an S-R flip-flop to be SET or RESET, the respective input must be __________.
Options- A. LOW
- B. HIGH
- C. installed with steering diodes
- D. in parallel with a limiting resistor Discuss
- 10. Two half adders can be combined to form a full adder with no additional gates.
Options- A. True
- B. False Discuss
Flip-Flops and Timers problems
Search Results
Correct Answer: edge-triggered
Correct Answer: unpredictable
Correct Answer: 13
Correct Answer: bistable multivibrators
Correct Answer: a positive-transition pulse generator
Correct Answer: edges, levels, pulses
Correct Answer: master-slave
Correct Answer: binary storage register
Correct Answer: HIGH
Correct Answer: False
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