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Sequential Logic Circuits
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Question
A 4-bit PISO shift register that receives 4 bits of parallel data will shift to the ________ by ________ position(s) for each clock pulse.
Options
A. right, one
B. right, two
C. left, one
D. left, three
Correct Answer
right, one
Sequential Logic Circuits problems
Search Results
1. The mod-10 counter is also referred to as a ________ counter.
Options
A. decade
B. strobing
C. ring
D. BCD
Show Answer
Scratch Pad
Discuss
Correct Answer: decade
2. When two counters are cascaded, the overall mod number is equal to the __________ of their individual mod numbers.
Options
A. product
B. sum
C. log
D. reciprocal
Show Answer
Scratch Pad
Discuss
Correct Answer: product
3. A sequence of equally spaced timing pulses may be easily generated by a(n) __________.
Options
A. ring counter
B. johnson counter
C. binary up counter
D. ripple counter
Show Answer
Scratch Pad
Discuss
Correct Answer: ring counter
4. Ring and johnson counters are _______.
Options
A. asynchronous counters
B. synchronous counters
C. true binary counters
D. asynchronous and true binary counters
Show Answer
Scratch Pad
Discuss
Correct Answer: synchronous counters
5. Synchronous construction reduces the delay time of a counter to the delay of __________.
Options
A. all flip-flops and gates
B. a single flip-flop and a gate
C. all flip-flops and gates after a 3 count
D. a single gate
Show Answer
Scratch Pad
Discuss
Correct Answer: a single flip-flop and a gate
6. An SRAM storage cell is less complex than a DRAM storage cell.
Options
A. True
B. False
Show Answer
Scratch Pad
Discuss
Correct Answer: False
7. When a binary word is stored in a memory location of a ROM, the process is called burning in.
Options
A. True
B. False
Show Answer
Scratch Pad
Discuss
Correct Answer: True
8. ROM stands for read-only memory.
Options
A. True
B. False
Show Answer
Scratch Pad
Discuss
Correct Answer: True
9. Memory configuration refers to the organization of storage bits within a memory.
Options
A. True
B. False
Show Answer
Scratch Pad
Discuss
Correct Answer: True
10. To avoid data loss, SRAM must be refreshed every few milliseconds.
Options
A. True
B. False
Show Answer
Scratch Pad
Discuss
Correct Answer: False
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