Which of the circuits in figure (a to d) is the sum-of-products implementation o

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Question
Which of the circuits in figure (a to d) is the sum-of-products implementation of figure (e)?
Options
A. a
B. b
C. c
D. d

Correct Answer

d

Combinational Logic Circuits problems

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1. A logic probe is placed on the output of a gate and the display indicator is dim. A pulser is used on each of the input terminals, but the output indication does not change. What is wrong?
Options
A. The output of the gate appears to be open.
B. The dim indication on the logic probe indicates that the supply voltage is probably low.
C. The dim indication is a result of a bad ground connection on the logic probe.
D. The gate may be a tristate device.

2. For the device shown here, assume the D input is LOW, both S inputs are LOW, and the input is LOW. What is the status of the outputs?
Options
A. All are HIGH.
B. All are LOW.
C. All but are LOW.
D. All but are HIGH.

3. What is the indication of a short on the input of a load gate?
Options
A. Only the output of the defective gate is affected.
B. There is a signal loss to all gates on the node.
C. The affected node will be stuck in the LOW state.
D. There is a signal loss to all gates on the node, and the affected node will be stuck in the LOW state.

4. As a technician you are confronted with a TTL circuit board containing dozens of IC chips. You have taken several readings at numerous IC chips, but the readings are inconclusive because of their erratic nature. Of the possible faults listed, select the one that most probably is causing the problem.
Options
A. A defective IC chip that is drawing excessive current from the power supply
B. A solar bridge between the inputs on the first IC chip on the board
C. An open input on the first IC chip on the board
D. A defective output IC chip that has an internal open to V_cc

9. What is the indication of a short to ground in the output of a driving gate?
Options
A. Only the output of the defective gate is affected.
B. There is a signal loss to all load gates.
C. The node may be stuck in either the HIGH or the LOW state.
D. The affected node will be stuck in the HIGH state.

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