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Home Digital Electronics MSI Logic Circuits See What Others Are Saying!
  • Question
  • What type of device is shown in the given figure, and what inputs (A3,A2,A1,A0) are required to produce the output levels as shown?

    What type of device is shown in the given figure, and what inputs (A3,A2,A1,A0) are required to prod


  • Options
  • A. A binary-to-decimal encoder; 0,1,1,1
  • B. A decimal-to-binary decoder; 1,1,1,0
  • C. A BCD-to-decimal decoder; 0,1,1,1
  • D. A decimal-to-BCD encoder; 1,1,1,0

  • Correct Answer
  • A BCD-to-decimal decoder; 0,1,1,1 


  • More questions

    • 1. EEPROM and Flash memory are electrically erasable.

    • Options
    • A. True
    • B. False
    • Discuss
    • 2. The binary adder circuit is designed to add ________ binary number(s) at a time.

    • Options
    • A. 1
    • B. 3
    • C. 2
    • D. 5
    • Discuss
    • 3. A logic circuit that can store one bit of information is a ________.

    • Options
    • A. flip-flop
    • B. counter
    • C. gate
    • D. code converter
    • Discuss
    • 4. All inputs to the MAX7000S device and all macrocell outputs feed the ________.

    • Options
    • A. LUT
    • B. PIA
    • C. LAB
    • D. PIA and LAB
    • Discuss
    • 5. How many BCD adders would be required to add the numbers 97310 + 3910?

    • Options
    • A. 3
    • B. 4
    • C. 5
    • D. 6
    • Discuss
    • 6. Depending on the ________ the IC is in, the output of the stepper motor HDL will respond to each pulse by changing state.

    • Options
    • A. mode
    • B. make
    • C. input
    • D. output
    • Discuss
    • 7. A positive binary number is represented by a 1 sign bit.

    • Options
    • A. True
    • B. False
    • Discuss
    • 8. In Boolean algebra, A + 1 = 1.

    • Options
    • A. True
    • B. False
    • Discuss
    • 9. The IEEE/ANSI notation of an internal underlined diamond denotes:

    • Options
    • A. totem-pole outputs.
    • B. open-collector outputs.
    • C. quadrature amplifiers.
    • D. tristate buffers.
    • Discuss
    • 10. In the frequency counter, the control clock is derived from the ________ by frequency dividers controlled in the control and timing block.

    • Options
    • A. BCD counters
    • B. system clock signal
    • C. display register
    • D. decoder/display
    • Discuss


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