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Home Digital Electronics MSI Logic Circuits See What Others Are Saying!
  • Question
  • Refer to the figure given below. The logic function generator being implemented with the multiplexer in this circuit produces a constant LOW on the output. The ABC inputs are checked and appear to be pulsing; also, the 0?7 and EN inputs are checked with the scope and all appear to be at 0 V. A check with the DMM confirms that power is on. What is the problem, and what should be done to correct it?

    Refer to the figure given below. The logic function generator being implemented with the multiplexer


  • Options
  • A. The output is shorted to Vcc; replace the IC.
  • B. The scope's vertical input is in the AC mode and the common connection for the 0,2,3 and 5 inputs is bad. Set the scope's vertical input mode to DC, and repair the bad solder connection.
  • C. Power has not been applied to the circuit; apply power.
  • D. The output is shorted to ground; replace the IC.

  • Correct Answer
  • The scope's vertical input is in the AC mode and the common connection for the 0,2,3 and 5 inputs is bad. Set the scope's vertical input mode to DC, and repair the bad solder connection. 


  • More questions

    • 1. EEPROM and Flash memory are electrically erasable.

    • Options
    • A. True
    • B. False
    • Discuss
    • 2. The binary adder circuit is designed to add ________ binary number(s) at a time.

    • Options
    • A. 1
    • B. 3
    • C. 2
    • D. 5
    • Discuss
    • 3. A logic circuit that can store one bit of information is a ________.

    • Options
    • A. flip-flop
    • B. counter
    • C. gate
    • D. code converter
    • Discuss
    • 4. All inputs to the MAX7000S device and all macrocell outputs feed the ________.

    • Options
    • A. LUT
    • B. PIA
    • C. LAB
    • D. PIA and LAB
    • Discuss
    • 5. How many BCD adders would be required to add the numbers 97310 + 3910?

    • Options
    • A. 3
    • B. 4
    • C. 5
    • D. 6
    • Discuss
    • 6. Depending on the ________ the IC is in, the output of the stepper motor HDL will respond to each pulse by changing state.

    • Options
    • A. mode
    • B. make
    • C. input
    • D. output
    • Discuss
    • 7. A positive binary number is represented by a 1 sign bit.

    • Options
    • A. True
    • B. False
    • Discuss
    • 8. In Boolean algebra, A + 1 = 1.

    • Options
    • A. True
    • B. False
    • Discuss
    • 9. The IEEE/ANSI notation of an internal underlined diamond denotes:

    • Options
    • A. totem-pole outputs.
    • B. open-collector outputs.
    • C. quadrature amplifiers.
    • D. tristate buffers.
    • Discuss
    • 10. In the frequency counter, the control clock is derived from the ________ by frequency dividers controlled in the control and timing block.

    • Options
    • A. BCD counters
    • B. system clock signal
    • C. display register
    • D. decoder/display
    • Discuss


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