Discussion
Home ‣ Digital Electronics ‣ Shift Registers Comments
- Question
Ring shift and Johnson counters are:
Options- A. synchronous counters
- B. aynchronous counters
- C. true binary counters
- D. synchronous and true binary counters
- Correct Answer
- synchronous counters
- 1. With a 50 kHz clock frequency, six bits can be serially entered into a shift register in ________.
Options- A. 12 µs
- B. 120 µs
- C. 12 ms
- D. 120 ms Discuss
- 2. When 1100010 is divided by 0101, what is the decimal remainder?
Options- A. 2
- B. 3
- C. 4
- D. 6 Discuss
- 3. What is one disadvantage of the ripple-carry adder?
Options- A. The interconnections are more complex.
- B. More stages are required to a full adder.
- C. It is slow due to propagation time.
- D. All of the above. Discuss
- 4. The summing outputs of a half- or full-adder are designated by which Greek symbol?
Options- A. omega
- B. theta
- C. lambda
- D. sigma Discuss
- 5. How many inputs must a full-adder have?
Options- A. 2
- B. 3
- C. 4
- D. 5 Discuss
- 6. How is a strobe signal used when serially loading a shift register?
Options- A. to turn the register on and off
- B. to control the number of clocks
- C. to determine which output Qs are used
- D. to determine the FFs that will be used Discuss
- 7. What is a shift register that will accept a parallel input, or a bidirectional serial load and internal shift features, called?
Options- A. tristate
- B. end around
- C. universal
- D. conversion Discuss
- 8. On the fifth clock pulse, a 4-bit Johnson sequence is Q0 = 0, Q1 = 1, Q2 = 1, and Q3 = 1. On the sixth clock pulse, the sequence is ________.
Options- A. Q0 = 1, Q1 = 0, Q2 = 0, Q3 = 0
- B. Q0 = 1, Q1 = 1, Q2 = 1, Q3 = 0
- C. Q0 = 0, Q1 = 0, Q2 = 1, Q3 = 1
- D. Q0 = 0, Q1 = 0, Q2 = 0, Q3 = 1 Discuss
- 9. Which type of device may be used to interface a parallel data format with external equipment's serial format?
Options- A. key matrix
- B. UART
- C. memory chip
- D. series in, parallel out Discuss
- 10. A 4-bit shift register that receives 4 bits of parallel data will shift to the ________ by ________ position(s) for each clock pulse.
Options- A. right, one
- B. right, two
- C. left, one
- D. left, three Discuss
Shift Registers problems
Search Results
Correct Answer: 120 µs
Correct Answer: 3
Correct Answer: It is slow due to propagation time.
Correct Answer: sigma
Correct Answer: 3
Correct Answer: to control the number of clocks
Correct Answer: universal
Correct Answer: Q0 = 0, Q1 = 0, Q2 = 1, Q3 = 1
Correct Answer: UART
Correct Answer: right, one
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