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  • Question
  • Sample-and-hold circuits in analog-to digital converters (ADCs) are designed to:


  • Options
  • A. sample and hold the output of the binary counter during the conversion process
  • B. stabilize the comparator's threshold voltage during the conversion process
  • C. stabilize the input analog signal during the conversion process
  • D. sample and hold the D/A converter staircase waveform during the conversion process

  • Correct Answer
  • stabilize the input analog signal during the conversion process 


  • Analog and Digital Converters problems


    Search Results


    • 1. Which is not an analog-to-digital (ADC) conversion error?

    • Options
    • A. differential nonlinearity
    • B. missing code
    • C. incorrect code
    • D. offset
    • Discuss
    • 2. What is the major advantage of the R/2R ladder digital-to-analog (DAC), as compared to a binary-weighted digital-to-analog DAC converter?

    • Options
    • A. It only uses two different resistor values.
    • B. It has fewer parts for the same number of inputs.
    • C. Its operation is much easier to analyze.
    • D. The virtual ground is eliminated and the circuit is therefore easier to understand and troubleshoot.
    • Discuss
    • 3. What is the resolution of a digital-to-analog converter (DAC)?

    • Options
    • A. It is the comparison between the actual output of the converter and its expected output.
    • B. It is the deviation between the ideal straight-line output and the actual output of the converter.
    • C. It is the smallest analog output change that can occur as a result of an increment in the digital input.
    • D. It is its ability to resolve between forward and reverse steps when sequenced over its entire range.
    • Discuss
    • 4. The difference between analog voltage represented by two adjacent digital codes, or the analog step size, is the:

    • Options
    • A. quantization
    • B. accuracy
    • C. resolution
    • D. monotonicity
    • Discuss
    • 5. The practical use of binary-weighted digital-to-analog converters is limited to:

    • Options
    • A. R/2R ladder D/A converters
    • B. 4-bit D/A converters
    • C. 8-bit D/A converters
    • D. op-amp comparators
    • Discuss
    • 6. In a flash analog-to-digital converter, the output of each comparator is connected to an input of a:

    • Options
    • A. decoder
    • B. priority encoder
    • C. multiplexer
    • D. demultiplexer
    • Discuss
    • 7. If a branch opens in a parallel circuit, the current in the remaining parallel paths will change.

    • Options
    • A. True
    • B. False
    • Discuss
    • 8. The largest branch resistance in a parallel circuit carries the largest branch current.

    • Options
    • A. True
    • B. False
    • Discuss
    • 9. Current divider predicts that the most current will flow in the parallel path of the most resistance.

    • Options
    • A. True
    • B. False
    • Discuss
    • 10. The total resistance of a parallel circuit is always greater than the largest resistor value.

    • Options
    • A. True
    • B. False
    • Discuss


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