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Home Electronics Flip-Flops and Timers Comments

  • Question
  • Which of the following is correct for a gated D-type flip-flop?


  • Options
  • A. The Q output is either SET or RESET as soon as the D input goes HIGH or LOW.
  • B. The output complement follows the input when enabled.
  • C. Only one of the inputs can be HIGH at a time.
  • D. The output toggles if one of the inputs is held HIGH.

  • Correct Answer
  • The Q output is either SET or RESET as soon as the D input goes HIGH or LOW. 


  • Flip-Flops and Timers problems


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    • 1. Latches constructed with NOR and NAND gates tend to remain in the latched condition due to which configuration feature?

    • Options
    • A. asynchronous operation
    • B. low input voltages
    • C. gate impedance
    • D. cross coupling
    • Discuss
    • 2. What is the significance of the J and K terminals on the J-K flip-flop?

    • Options
    • A. There is no known significance in their designations.
    • B. The J represents "jump," which is how the Q output reacts whenever the clock goes HIGH and the J input is also HIGH.
    • C. The letters represent the initials of Johnson and King, the co-inventors of the J-K flip-flop.
    • D. All of the other letters of the alphabet are already in use.
    • Discuss
    • 3. If both inputs of an S-R NAND latch are LOW, what will happen to the output?

    • Options
    • A. The output would become unpredictable.
    • B. The output will toggle.
    • C. The output will reset.
    • D. No change will occur in the output.
    • Discuss
    • 4. A basic S-R flip-flop can be constructed by cross-coupling which basic logic gates?

    • Options
    • A. AND or OR gates
    • B. XOR or XNOR gates
    • C. NOR or NAND gates
    • D. AND or NOR gates
    • Discuss
    • 5. What is another name for a one-shot?

    • Options
    • A. monostable
    • B. bistable
    • C. astable
    • D. tristable
    • Discuss
    • 6. Which of the following describes the operation of a positive edge-triggered D-type flip-flop?

    • Options
    • A. If both inputs are HIGH, the output will toggle.
    • B. The output will follow the input on the leading edge of the clock.
    • C. When both inputs are LOW, an invalid state exists.
    • D. The input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock.
    • Discuss
    • 7. When both inputs of a J-K flip-flop cycle, the output will:

    • Options
    • A. be invalid
    • B. not change
    • C. change
    • D. toggle
    • Discuss
    • 8. Use the two's complement system to add the signed numbers 11110010 and 11110011. Determine, in decimal, the sign and value of each number and their sum.

    • Options
    • A. ?14 and ?13; ?27
    • B. ?113 and ?114; 227
    • C. ?27 and ?13; 40
    • D. ?11 and ?16; ?27
    • Discuss
    • 9. Adding the two's complement of ?11 + (?2) will yield which two's complement answer?

    • Options
    • A. 1110 1101
    • B. 1111 1001
    • C. 1111 0011
    • D. 1110 1001
    • Discuss
    • 10. The fast carry or look-ahead carry circuits found in most 4-bit parallel-adder circuits:

    • Options
    • A. increase ripple delay
    • B. add a 1 to complemented inputs
    • C. reduce propagation delay
    • D. determine sign and magnitude
    • Discuss


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