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- Question
If both inputs of an S-R NAND latch are LOW, what will happen to the output?
Options- A. The output would become unpredictable.
- B. The output will toggle.
- C. The output will reset.
- D. No change will occur in the output.
- Correct Answer
- The output would become unpredictable.
- 1. A basic S-R flip-flop can be constructed by cross-coupling which basic logic gates?
Options- A. AND or OR gates
- B. XOR or XNOR gates
- C. NOR or NAND gates
- D. AND or NOR gates Discuss
- 2. What is another name for a one-shot?
Options- A. monostable
- B. bistable
- C. astable
- D. tristable Discuss
- 3. An astable multivibrator is a circuit that:
Options- A. has two stable states
- B. is free-running
- C. produces a continuous output signal
- D. is free-running and produces a continuous output signal Discuss
- 4. What is one disadvantage of an S-R flip-flop?
Options- A. It has no Enable input.
- B. It has a RACE condition.
- C. It has no clock input.
- D. It has only a single output. Discuss
- 5. The equation for the output frequency of a 555 timer operating in the astable mode is:
.
What value of C1 will be required if R1 = 1 kΩ, R2 = 1 kΩ, and f = 1 kHz?
Options- A. 0.33 µF
- B. 0.48 µF
- C. 480 µF
- D. 33 nF Discuss
- 6. What is the significance of the J and K terminals on the J-K flip-flop?
Options- A. There is no known significance in their designations.
- B. The J represents "jump," which is how the Q output reacts whenever the clock goes HIGH and the J input is also HIGH.
- C. The letters represent the initials of Johnson and King, the co-inventors of the J-K flip-flop.
- D. All of the other letters of the alphabet are already in use. Discuss
- 7. Latches constructed with NOR and NAND gates tend to remain in the latched condition due to which configuration feature?
Options- A. asynchronous operation
- B. low input voltages
- C. gate impedance
- D. cross coupling Discuss
- 8. Which of the following is correct for a gated D-type flip-flop?
Options- A. The Q output is either SET or RESET as soon as the D input goes HIGH or LOW.
- B. The output complement follows the input when enabled.
- C. Only one of the inputs can be HIGH at a time.
- D. The output toggles if one of the inputs is held HIGH. Discuss
- 9. Which of the following describes the operation of a positive edge-triggered D-type flip-flop?
Options- A. If both inputs are HIGH, the output will toggle.
- B. The output will follow the input on the leading edge of the clock.
- C. When both inputs are LOW, an invalid state exists.
- D. The input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock. Discuss
- 10. When both inputs of a J-K flip-flop cycle, the output will:
Options- A. be invalid
- B. not change
- C. change
- D. toggle Discuss
Flip-Flops and Timers problems
Search Results
Correct Answer: NOR or NAND gates
Correct Answer: monostable
Correct Answer: produces a continuous output signal
Correct Answer: It has a RACE condition.
Correct Answer: 0.48 µF
Correct Answer: There is no known significance in their designations.
Correct Answer: cross coupling
Correct Answer: The Q output is either SET or RESET as soon as the D input goes HIGH or LOW.
Correct Answer: The output will follow the input on the leading edge of the clock.
Correct Answer: not change
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