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- Question
Synchronous counters eliminate the delay problems encountered with asynchronous (ripple) counters because the:
Options- A. input clock pulses are applied only to the first and last stages
- B. input clock pulses are applied only to the last stage
- C. input clock pulses are not used to activate any of the counter stages
- D. input clock pulses are applied simultaneously to each stage
- Correct Answer
- input clock pulses are applied simultaneously to each stage
- 1. What is a shift register that will accept a parallel input and can shift data left or right called?
Options- A. tri-state
- B. end around
- C. bidirectional universal
- D. conversion Discuss
- 2. A sequence of equally spaced timing pulses may be easily generated by which type of counter circuit?
Options- A. shift register sequencer
- B. clock
- C. johnson
- D. binary Discuss
- 3. A ripple counter's speed is limited by the propagation delay of:
Options- A. each flip-flop
- B. all flip-flops and gates
- C. the flip-flops only with gates
- D. only circuit gates Discuss
- 4. To operate correctly, starting a ring counter requires:
Options- A. clearing all the flip-flops
- B. presetting one flip-flop and clearing all the others
- C. clearing one flip-flop and presetting all the others
- D. presetting all the flip-flops Discuss
- 5. What type of register would shift a complete binary number in one bit at a time and shift all the stored bits out one bit at a time?
Options- A. PIPO
- B. SISO
- C. SIPO
- D. PISO Discuss
- 6. Which type of device may be used to interface a parallel data format with external equipment's serial format?
Options- A. key matrix
- B. UART
- C. memory chip
- D. serial-in, parallel-out Discuss
- 7. What is meant by parallel-loading the register?
Options- A. Shifting the data in all flip-flops simultaneously
- B. Loading data in two of the flip-flops
- C. Loading data in all four flip-flops at the same time
- D. Momentarily disabling the synchronous SET and RESET inputs Discuss
- 8. Which of the following memories uses a MOSFET and a capacitor as its memory cell?
Options- A. SRAM
- B. DRAM
- C. ROM
- D. DROM Discuss
- 9. The access time (tacc) of a memory IC is governed by the IC's:
Options- A. internal address buffer
- B. internal address decoder
- C. volatility
- D. internal address decoder and volatility Discuss
- 10. What is the principal advantage of using address multiplexing with DRAM memory?
Options- A. reduced memory access time
- B. reduced requirement for constant refreshing of the memory contents
- C. reduced pin count and decrease in package size
- D. no requirement for a chip-select input line, thereby reducing the pin count Discuss
Sequential Logic Circuits problems
Search Results
Correct Answer: bidirectional universal
Correct Answer: shift register sequencer
Correct Answer: each flip-flop
Correct Answer: presetting one flip-flop and clearing all the others
Correct Answer: SISO
Correct Answer: UART
Correct Answer: Loading data in all four flip-flops at the same time
Correct Answer: DRAM
Correct Answer: internal address decoder
Correct Answer: reduced pin count and decrease in package size
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