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- Question
A sequence of equally spaced timing pulses may be easily generated by which type of counter circuit?
Options- A. shift register sequencer
- B. clock
- C. johnson
- D. binary
- Correct Answer
- shift register sequencer
- 1. A ripple counter's speed is limited by the propagation delay of:
Options- A. each flip-flop
- B. all flip-flops and gates
- C. the flip-flops only with gates
- D. only circuit gates Discuss
- 2. To operate correctly, starting a ring counter requires:
Options- A. clearing all the flip-flops
- B. presetting one flip-flop and clearing all the others
- C. clearing one flip-flop and presetting all the others
- D. presetting all the flip-flops Discuss
- 3. What type of register would shift a complete binary number in one bit at a time and shift all the stored bits out one bit at a time?
Options- A. PIPO
- B. SISO
- C. SIPO
- D. PISO Discuss
- 4. One of the major drawbacks to the use of asynchronous counters is that:
Options- A. low-frequency applications are limited because of internal propagation delays
- B. high-frequency applications are limited because of internal propagation delays
- C. Asynchronous counters do not have major drawbacks and are suitable for use in high- and low-frequency counting applications.
- D. Asynchronous counters do not have propagation delays, which limits their use in high-frequency applications. Discuss
- 5. What happens to the parallel output word in an asynchronous binary down counter whenever a clock pulse occurs?
Options- A. The output word decreases by 1.
- B. The output word decreases by 2.
- C. The output word increases by 1.
- D. The output word increases by 2. Discuss
- 6. What is a shift register that will accept a parallel input and can shift data left or right called?
Options- A. tri-state
- B. end around
- C. bidirectional universal
- D. conversion Discuss
- 7. Synchronous counters eliminate the delay problems encountered with asynchronous (ripple) counters because the:
Options- A. input clock pulses are applied only to the first and last stages
- B. input clock pulses are applied only to the last stage
- C. input clock pulses are not used to activate any of the counter stages
- D. input clock pulses are applied simultaneously to each stage Discuss
- 8. Which type of device may be used to interface a parallel data format with external equipment's serial format?
Options- A. key matrix
- B. UART
- C. memory chip
- D. serial-in, parallel-out Discuss
- 9. What is meant by parallel-loading the register?
Options- A. Shifting the data in all flip-flops simultaneously
- B. Loading data in two of the flip-flops
- C. Loading data in all four flip-flops at the same time
- D. Momentarily disabling the synchronous SET and RESET inputs Discuss
- 10. Which of the following memories uses a MOSFET and a capacitor as its memory cell?
Options- A. SRAM
- B. DRAM
- C. ROM
- D. DROM Discuss
Sequential Logic Circuits problems
Search Results
Correct Answer: each flip-flop
Correct Answer: presetting one flip-flop and clearing all the others
Correct Answer: SISO
Correct Answer: high-frequency applications are limited because of internal propagation delays
Correct Answer: The output word decreases by 1.
Correct Answer: bidirectional universal
Correct Answer: input clock pulses are applied simultaneously to each stage
Correct Answer: UART
Correct Answer: Loading data in all four flip-flops at the same time
Correct Answer: DRAM
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