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  • Question
  • What type of register would shift a complete binary number in one bit at a time and shift all the stored bits out one bit at a time?


  • Options
  • A. PIPO
  • B. SISO
  • C. SIPO
  • D. PISO

  • Correct Answer
  • SISO 


  • Sequential Logic Circuits problems


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    • 1. One of the major drawbacks to the use of asynchronous counters is that:

    • Options
    • A. low-frequency applications are limited because of internal propagation delays
    • B. high-frequency applications are limited because of internal propagation delays
    • C. Asynchronous counters do not have major drawbacks and are suitable for use in high- and low-frequency counting applications.
    • D. Asynchronous counters do not have propagation delays, which limits their use in high-frequency applications.
    • Discuss
    • 2. What happens to the parallel output word in an asynchronous binary down counter whenever a clock pulse occurs?

    • Options
    • A. The output word decreases by 1.
    • B. The output word decreases by 2.
    • C. The output word increases by 1.
    • D. The output word increases by 2.
    • Discuss
    • 3. A comparison between ring and johnson counters indicates that:

    • Options
    • A. a ring counter has fewer flip-flops but requires more decoding circuitry
    • B. a ring counter has an inverted feedback path
    • C. a johnson counter has more flip-flops but less decoding circuitry
    • D. a johnson counter has an inverted feedback path
    • Discuss
    • 4. When the output of a tri-state shift register is disabled, the output level is placed in a:

    • Options
    • A. float state
    • B. LOW state
    • C. high impedance state
    • D. float state and a high impedance state
    • Discuss
    • 5. Mod-6 and mod-12 counters are most commonly used in:

    • Options
    • A. frequency counters
    • B. multiplexed displays
    • C. digital clocks
    • D. power consumption meters
    • Discuss
    • 6. To operate correctly, starting a ring counter requires:

    • Options
    • A. clearing all the flip-flops
    • B. presetting one flip-flop and clearing all the others
    • C. clearing one flip-flop and presetting all the others
    • D. presetting all the flip-flops
    • Discuss
    • 7. A ripple counter's speed is limited by the propagation delay of:

    • Options
    • A. each flip-flop
    • B. all flip-flops and gates
    • C. the flip-flops only with gates
    • D. only circuit gates
    • Discuss
    • 8. A sequence of equally spaced timing pulses may be easily generated by which type of counter circuit?

    • Options
    • A. shift register sequencer
    • B. clock
    • C. johnson
    • D. binary
    • Discuss
    • 9. What is a shift register that will accept a parallel input and can shift data left or right called?

    • Options
    • A. tri-state
    • B. end around
    • C. bidirectional universal
    • D. conversion
    • Discuss
    • 10. Synchronous counters eliminate the delay problems encountered with asynchronous (ripple) counters because the:

    • Options
    • A. input clock pulses are applied only to the first and last stages
    • B. input clock pulses are applied only to the last stage
    • C. input clock pulses are not used to activate any of the counter stages
    • D. input clock pulses are applied simultaneously to each stage
    • Discuss


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