Speed–power product — how do you calculate it for a logic family? Select the correct method for computing the speed–power product (a common figure of merit) of a logic gate or family.

Introduction / Context:
The speed–power product (SPP) is a widely used figure of merit to compare logic families. It captures the trade-off between how fast a gate switches (propagation delay) and how much power it consumes. A lower SPP indicates better efficiency: faster operation per unit of power.

Given Data / Assumptions:

• Propagation delay is typically specified in nanoseconds for logic gates.
• Power dissipation is typically given in milliwatts under specified conditions.
• We want a simple multiplicative metric.

Concept / Approach:
Multiply the typical propagation delay (ns) by the typical power dissipation (mW). The product has units of nJ/s? Interpreted more practically, ns * mW = picojoules (since mW = mJ/s and ns scales time), which reflects the energy per switching event under certain simplifying assumptions. Families with lower SPP achieve shorter delays with less power.

Step-by-Step Solution:

Verification / Alternative check:
Example: A gate with tp = 10 ns and PD = 10 mW has SPP = 100 ns·mW (≈ 100 pJ). A gate with tp = 5 ns and PD = 40 mW has SPP = 200 ns·mW—faster but less efficient by this metric.

Why Other Options Are Wrong:

• Using µs, ms, or µW mixes unrealistic units for modern logic comparisons.
• Dividing power by delay is not the standard definition.

Common Pitfalls:

• Comparing SPP values taken at different voltages/temperatures; ensure consistent conditions.

Final Answer:
The propagation delay in ns is multiplied by the power dissipation in mW.