Ripple-carry adder limitation: What is a primary disadvantage of the ripple-carry adder architecture when compared with faster adder structures?

Introduction / Context:
Adder design strongly influences CPU cycle time. The ripple-carry adder (RCA) is simple and area-efficient but suffers from worst-case delay proportional to bit-width. This question identifies the chief drawback.

Given Data / Assumptions:

• Adder built by cascading full-adder stages.
• Each stage must wait for the carry from the previous stage.
• No special carry acceleration is present.

Concept / Approach:
Because each carry must ripple through all preceding stages, the overall delay grows linearly with the number of bits. This makes RCAs slow compared with carry-look-ahead or prefix adders.

Step-by-Step Solution:
Model delay: T_total ≈ n * t_carry + t_sum(msb).As n increases, T_total increases linearly.Hence, the principal disadvantage is speed (propagation delay), not interconnect complexity.

Verification / Alternative check:
Performance-optimized designs employ carry-look-ahead, carry-select, or parallel-prefix adders to reduce the carry chain depth.

Why Other Options Are Wrong:
Interconnections are simpler, not more complex, than advanced adders.The number of stages equals the bit-width; it is not “more stages to a full adder.”“All of the above” is false because only the speed disadvantage is correct.RCAs can be cascaded to arbitrary widths; they just become slower.

Common Pitfalls:
Confusing simplicity (an RCA is easy to wire) with performance advantages; they are often opposites.

Final Answer:
It is slow due to propagation time.